TY - GEN
T1 - A multi-axis readout circuit using in female ovulation monitoring platform
AU - Yu, Hsin Yi
AU - Lai, Kelvin Yi Tse
AU - Chang, Hsie-Chia
AU - Lee, Chen-Yi
PY - 2016/5/31
Y1 - 2016/5/31
N2 - In this paper, an energy-efficient monitor, including three capacitive and two resistive readout circuits with hardware-sharing architecture, is presented for female ovulation. The proposed design is featuring two calibration modules: one decreases the initial offset by capacitor array, and the other reduces P-V-T variations by taking proportion between sensing and ruler results. After implemented in UMC 0.18μm CMOS-MEMS technology, the post-layout simulation results show that our circuit consumes 30μW and 49μW in 0.8ms conversion time under 1.8V supplied voltage for 1-axis and 3-axis. The capacitive resolution is around 0.1fF and the sensing range of die-temperature is 0~100°C with 0.05°C resolution.
AB - In this paper, an energy-efficient monitor, including three capacitive and two resistive readout circuits with hardware-sharing architecture, is presented for female ovulation. The proposed design is featuring two calibration modules: one decreases the initial offset by capacitor array, and the other reduces P-V-T variations by taking proportion between sensing and ruler results. After implemented in UMC 0.18μm CMOS-MEMS technology, the post-layout simulation results show that our circuit consumes 30μW and 49μW in 0.8ms conversion time under 1.8V supplied voltage for 1-axis and 3-axis. The capacitive resolution is around 0.1fF and the sensing range of die-temperature is 0~100°C with 0.05°C resolution.
KW - Capacitive and Resistive Readout Circuits
KW - Female Ovulation Monitoring Platform
KW - Time-to-Digital Converter
UR - http://www.scopus.com/inward/record.url?scp=84978406303&partnerID=8YFLogxK
U2 - 10.1109/VLSI-DAT.2016.7482544
DO - 10.1109/VLSI-DAT.2016.7482544
M3 - Conference contribution
AN - SCOPUS:84978406303
T3 - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
BT - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
Y2 - 25 April 2016 through 27 April 2016
ER -