A multi-axis readout circuit using in female ovulation monitoring platform

Hsin Yi Yu; Kelvin Yi Tse Lai; Hsie-Chia Chang; Chen-Yi Lee

doi:10.1109/VLSI-DAT.2016.7482544

A multi-axis readout circuit using in female ovulation monitoring platform

Hsin Yi Yu, Kelvin Yi Tse Lai, Hsie-Chia Chang, Chen-Yi Lee

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

In this paper, an energy-efficient monitor, including three capacitive and two resistive readout circuits with hardware-sharing architecture, is presented for female ovulation. The proposed design is featuring two calibration modules: one decreases the initial offset by capacitor array, and the other reduces P-V-T variations by taking proportion between sensing and ruler results. After implemented in UMC 0.18μm CMOS-MEMS technology, the post-layout simulation results show that our circuit consumes 30μW and 49μW in 0.8ms conversion time under 1.8V supplied voltage for 1-axis and 3-axis. The capacitive resolution is around 0.1fF and the sensing range of die-temperature is 0~100°C with 0.05°C resolution.

Original language	English
Title of host publication	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467394987
DOIs	https://doi.org/10.1109/VLSI-DAT.2016.7482544
State	Published - 31 May 2016
Event	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan Duration: 25 Apr 2016 → 27 Apr 2016

Publication series

Name	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Conference

Conference	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
Country/Territory	Taiwan
City	Hsinchu
Period	25/04/16 → 27/04/16

Keywords

Capacitive and Resistive Readout Circuits
Female Ovulation Monitoring Platform
Time-to-Digital Converter

Access to Document

10.1109/VLSI-DAT.2016.7482544

Cite this

Yu, H. Y., Lai, K. Y. T., Chang, H.-C., & Lee, C.-Y. (2016). A multi-axis readout circuit using in female ovulation monitoring platform. In 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 Article 7482544 (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2016.7482544

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title = "A multi-axis readout circuit using in female ovulation monitoring platform",

abstract = "In this paper, an energy-efficient monitor, including three capacitive and two resistive readout circuits with hardware-sharing architecture, is presented for female ovulation. The proposed design is featuring two calibration modules: one decreases the initial offset by capacitor array, and the other reduces P-V-T variations by taking proportion between sensing and ruler results. After implemented in UMC 0.18μm CMOS-MEMS technology, the post-layout simulation results show that our circuit consumes 30μW and 49μW in 0.8ms conversion time under 1.8V supplied voltage for 1-axis and 3-axis. The capacitive resolution is around 0.1fF and the sensing range of die-temperature is 0~100°C with 0.05°C resolution.",

keywords = "Capacitive and Resistive Readout Circuits, Female Ovulation Monitoring Platform, Time-to-Digital Converter",

author = "Yu, {Hsin Yi} and Lai, {Kelvin Yi Tse} and Hsie-Chia Chang and Chen-Yi Lee",

year = "2016",

month = may,

day = "31",

doi = "10.1109/VLSI-DAT.2016.7482544",

language = "English",

series = "2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016",

address = "美國",

note = "2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 ; Conference date: 25-04-2016 Through 27-04-2016",

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Yu, HY, Lai, KYT, Chang, H-C & Lee, C-Y 2016, A multi-axis readout circuit using in female ovulation monitoring platform. in 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016., 7482544, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Institute of Electrical and Electronics Engineers Inc., 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Hsinchu, Taiwan, 25/04/16. https://doi.org/10.1109/VLSI-DAT.2016.7482544

A multi-axis readout circuit using in female ovulation monitoring platform. / Yu, Hsin Yi; Lai, Kelvin Yi Tse; Chang, Hsie-Chia et al.
2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7482544 (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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AU - Yu, Hsin Yi

AU - Lai, Kelvin Yi Tse

AU - Chang, Hsie-Chia

AU - Lee, Chen-Yi

PY - 2016/5/31

Y1 - 2016/5/31

N2 - In this paper, an energy-efficient monitor, including three capacitive and two resistive readout circuits with hardware-sharing architecture, is presented for female ovulation. The proposed design is featuring two calibration modules: one decreases the initial offset by capacitor array, and the other reduces P-V-T variations by taking proportion between sensing and ruler results. After implemented in UMC 0.18μm CMOS-MEMS technology, the post-layout simulation results show that our circuit consumes 30μW and 49μW in 0.8ms conversion time under 1.8V supplied voltage for 1-axis and 3-axis. The capacitive resolution is around 0.1fF and the sensing range of die-temperature is 0~100°C with 0.05°C resolution.

AB - In this paper, an energy-efficient monitor, including three capacitive and two resistive readout circuits with hardware-sharing architecture, is presented for female ovulation. The proposed design is featuring two calibration modules: one decreases the initial offset by capacitor array, and the other reduces P-V-T variations by taking proportion between sensing and ruler results. After implemented in UMC 0.18μm CMOS-MEMS technology, the post-layout simulation results show that our circuit consumes 30μW and 49μW in 0.8ms conversion time under 1.8V supplied voltage for 1-axis and 3-axis. The capacitive resolution is around 0.1fF and the sensing range of die-temperature is 0~100°C with 0.05°C resolution.

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KW - Time-to-Digital Converter

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Yu HY, Lai KYT, Chang HC , Lee CY. A multi-axis readout circuit using in female ovulation monitoring platform. In 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7482544. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016). doi: 10.1109/VLSI-DAT.2016.7482544

A multi-axis readout circuit using in female ovulation monitoring platform

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Keywords

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