A Monolithic GaN-Based Driver and GaN Power HEMT with Diode-Emulated GaN Technique for 50MHz Operation and Sub-0.2ns Deadtime Control

Yu Yung Kao, Tz Wun Wang, Sheng Hsi Hung, Yong Hwa Wen, Tzu Hsien Yang, Si Yi Li, Ke Horng Chen, Ying Hsi Lin, Shian Ru Lin, Tsung Yen Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Monolithic gallium-nitride (GaN) high-electron-mobility transistors (HEMTs) have become popular due to their low parasitic capacitance, low on-resistance (RON), and no reverse recovery charge loss for high-frequency and high-power-density applications [1]-[6]. However, GaN HEMTs have several process defects [7], such as trapping effect and reverse-conduction loss, which will reduce the efficiency of GaN-based converters. Referring to Fig. 14.1.1, during the deadtime, the VSW falls to negative voltage before low-side GaN HEMT (QL) becomes conductive. Even without a body diode, QL will experience 'self-commutation loss' when the voltage difference between its gate and drain exceeds the threshold voltage (VTH, E(650V)). The overall efficiency decreases since GaN HEMTs have higher source-to-drain voltage drop (VSD) as compared to the body diode voltage of silicon MOSFETs. Although the power converter presented in [5] uses adaptive deadtime control to achieve a 3% efficiency improvement, due to the unpredictable delay of discrete control, the load-dependent deadtime is still not well controlled. Moreover, considering high switching operation, high dVsw/dt will cause gate ringing problem in switching period. At bottom middle of Fig. 14.1.1, the conventional negative turn-off gate bias and high drain voltage will cause a large electric field between gate and drain, thereby inducing serious trapping effect (bottom left of Fig. 14.1.1). The monolithic GaN driver with adaptive source current (IlCTRL) does not consider the parasitic effects during turn-off period (bottom right of Fig. 14.1.1) [1].

Original languageEnglish
Title of host publication2022 IEEE International Solid-State Circuits Conference, ISSCC 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages228-230
Number of pages3
ISBN (Electronic)9781665428002
DOIs
StatePublished - 2022
Event2022 IEEE International Solid-State Circuits Conference, ISSCC 2022 - San Francisco, United States
Duration: 20 Feb 202226 Feb 2022

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume2022-February
ISSN (Print)0193-6530

Conference

Conference2022 IEEE International Solid-State Circuits Conference, ISSCC 2022
Country/TerritoryUnited States
CitySan Francisco
Period20/02/2226/02/22

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