A monolithic CMOS/MEMS accelerometer with zero-g calibration readout circuit

Yu Sian Liu; Chien Jo Huang; Fu Yen Kuo; Kuei-Ann Wen; Long Sheng Fan

doi:10.1109/EUROCON.2013.6625271

A monolithic CMOS/MEMS accelerometer with zero-g calibration readout circuit

Yu Sian Liu, Chien Jo Huang, Fu Yen Kuo, Kuei-Ann Wen, Long Sheng Fan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

A monolithic accelerometer design with zero-g calibration with TSMC 0.18 μm mixed-signal 1P6M process is presented. On-chip digital offset calibration enables compensation of random mechanical offset in the sensor due to process variation. The maximum 21 fF capacitance mismatch can be calibrated. The simulation results show that the whole system have 452.1 mV/g sensitivity. The power consumption is about 1.16 mW. The output noise is 26.85 μg/√Hz at 1KHz.

Original language	English
Title of host publication	IEEE EuroCon 2013
Pages	2106-2110
Number of pages	5
DOIs	https://doi.org/10.1109/EUROCON.2013.6625271
State	Published - 4 Dec 2013
Event	IEEE EuroCon 2013 - Zagreb, Croatia Duration: 1 Jul 2013 → 4 Jul 2013

Publication series

Name	IEEE EuroCon 2013

Conference

Conference	IEEE EuroCon 2013
Country/Territory	Croatia
City	Zagreb
Period	1/07/13 → 4/07/13

Keywords

Accelerometer capacitive readout
Offset calibration
Readout circuit
Zero-g calibration

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10.1109/EUROCON.2013.6625271

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title = "A monolithic CMOS/MEMS accelerometer with zero-g calibration readout circuit",

abstract = "A monolithic accelerometer design with zero-g calibration with TSMC 0.18 μm mixed-signal 1P6M process is presented. On-chip digital offset calibration enables compensation of random mechanical offset in the sensor due to process variation. The maximum 21 fF capacitance mismatch can be calibrated. The simulation results show that the whole system have 452.1 mV/g sensitivity. The power consumption is about 1.16 mW. The output noise is 26.85 μg/√Hz at 1KHz.",

keywords = "Accelerometer capacitive readout, Offset calibration, Readout circuit, Zero-g calibration",

author = "Liu, {Yu Sian} and Huang, {Chien Jo} and Kuo, {Fu Yen} and Kuei-Ann Wen and Fan, {Long Sheng}",

year = "2013",

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AU - Liu, Yu Sian

AU - Huang, Chien Jo

AU - Kuo, Fu Yen

AU - Wen, Kuei-Ann

AU - Fan, Long Sheng

PY - 2013/12/4

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N2 - A monolithic accelerometer design with zero-g calibration with TSMC 0.18 μm mixed-signal 1P6M process is presented. On-chip digital offset calibration enables compensation of random mechanical offset in the sensor due to process variation. The maximum 21 fF capacitance mismatch can be calibrated. The simulation results show that the whole system have 452.1 mV/g sensitivity. The power consumption is about 1.16 mW. The output noise is 26.85 μg/√Hz at 1KHz.

AB - A monolithic accelerometer design with zero-g calibration with TSMC 0.18 μm mixed-signal 1P6M process is presented. On-chip digital offset calibration enables compensation of random mechanical offset in the sensor due to process variation. The maximum 21 fF capacitance mismatch can be calibrated. The simulation results show that the whole system have 452.1 mV/g sensitivity. The power consumption is about 1.16 mW. The output noise is 26.85 μg/√Hz at 1KHz.

KW - Accelerometer capacitive readout

KW - Offset calibration

KW - Readout circuit

KW - Zero-g calibration

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U2 - 10.1109/EUROCON.2013.6625271

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M3 - Conference contribution

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EP - 2110

BT - IEEE EuroCon 2013

T2 - IEEE EuroCon 2013

Y2 - 1 July 2013 through 4 July 2013

ER -

A monolithic CMOS/MEMS accelerometer with zero-g calibration readout circuit

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