A monolithic CMOS MEMS accelerometer with chopper correlated double sampling readout circuit

Chun Kai Wang; Che Sheng Chen; Kuei-Ann Wen

doi:10.1109/ISCAS.2011.5937993

A monolithic CMOS MEMS accelerometer with chopper correlated double sampling readout circuit

Chun Kai Wang^*, Che Sheng Chen, Kuei-Ann Wen

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

19 Scopus citations

Abstract

A monolithic CMOS MEMS capacitive accelerometer with micropower analog readout circuit is presented in this paper. In order to optimize noise-power performance of accelerometer in limited area, a specification driven MEMS/IC co-design flow is adopted. In analog readout circuit design, the proposed circuit architecture combines chopper stabilization and correlated double sampling to suppress low frequency noise and compensate DC offset. The RMS input referred noise voltage is 9.82 nV/Hz under 100Hz. The power consumption is 36uW at 100kHz modulation frequency.

Original language	English
Title of host publication	2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Pages	2023-2026
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2011.5937993
State	Published - 2 Aug 2011
Event	2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 - Rio de Janeiro, Brazil Duration: 15 May 2011 → 18 May 2011

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Country/Territory	Brazil
City	Rio de Janeiro
Period	15/05/11 → 18/05/11

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10.1109/ISCAS.2011.5937993

Cite this

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title = "A monolithic CMOS MEMS accelerometer with chopper correlated double sampling readout circuit",

abstract = "A monolithic CMOS MEMS capacitive accelerometer with micropower analog readout circuit is presented in this paper. In order to optimize noise-power performance of accelerometer in limited area, a specification driven MEMS/IC co-design flow is adopted. In analog readout circuit design, the proposed circuit architecture combines chopper stabilization and correlated double sampling to suppress low frequency noise and compensate DC offset. The RMS input referred noise voltage is 9.82 nV/Hz under 100Hz. The power consumption is 36uW at 100kHz modulation frequency.",

author = "Wang, {Chun Kai} and Chen, {Che Sheng} and Kuei-Ann Wen",

year = "2011",

month = aug,

day = "2",

doi = "10.1109/ISCAS.2011.5937993",

language = "English",

isbn = "9781424494736",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

pages = "2023--2026",

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note = "2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 ; Conference date: 15-05-2011 Through 18-05-2011",

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Wang, CK, Chen, CS & Wen, K-A 2011, A monolithic CMOS MEMS accelerometer with chopper correlated double sampling readout circuit. in 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011., 5937993, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 2023-2026, 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011, Rio de Janeiro, Brazil, 15/05/11. https://doi.org/10.1109/ISCAS.2011.5937993

A monolithic CMOS MEMS accelerometer with chopper correlated double sampling readout circuit. / Wang, Chun Kai; Chen, Che Sheng; Wen, Kuei-Ann.
2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011. 2011. p. 2023-2026 5937993 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - A monolithic CMOS MEMS capacitive accelerometer with micropower analog readout circuit is presented in this paper. In order to optimize noise-power performance of accelerometer in limited area, a specification driven MEMS/IC co-design flow is adopted. In analog readout circuit design, the proposed circuit architecture combines chopper stabilization and correlated double sampling to suppress low frequency noise and compensate DC offset. The RMS input referred noise voltage is 9.82 nV/Hz under 100Hz. The power consumption is 36uW at 100kHz modulation frequency.

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T3 - Proceedings - IEEE International Symposium on Circuits and Systems

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A monolithic CMOS MEMS accelerometer with chopper correlated double sampling readout circuit

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