A module generator for parameterized DSP core

Ya Lan Tsao; Yu Chun Lin; Wei Hao Chen; Bo Shiang Huang; Shyh-Jye Jou

doi:10.1109/APCCAS.2004.1412770

A module generator for parameterized DSP core

Ya Lan Tsao^*, Yu Chun Lin, Wei Hao Chen, Bo Shiang Huang, Shyh-Jye Jou

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

1 Scopus citations

Abstract

In this paper, a parameterized module generator of DSP core for embedded application is proposed. Some special functions for the communication applications are included in this DSP core. Moreover, key parameters of the DSP core are identified and analyzed to show their effects on performance index such as execution cycle, hardware gate count and power consumption. The parameters of the DSP core and the special functions required can be specified by user which is required by the application. The DSP core which generated by the generator is synthesizable and flexible RTL code for system integration. The turn around time of design process can be dramatically decreased. Furthermore, the generator can automatically optimize the structure of DSP core for different parameters. The design examples show that the variety of selection in implementation by using this parameterized generator and its flow provides the system designer to obtain better result in area, speed and power trade-off.

Original language	English
Pages	361-364
Number of pages	4
DOIs	https://doi.org/10.1109/APCCAS.2004.1412770
State	Published - Dec 2004
Event	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan Duration: 6 Dec 2004 → 9 Dec 2004

Conference

Conference	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
Country/Territory	Taiwan
City	Tainan
Period	6/12/04 → 9/12/04

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10.1109/APCCAS.2004.1412770

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title = "A module generator for parameterized DSP core",

abstract = "In this paper, a parameterized module generator of DSP core for embedded application is proposed. Some special functions for the communication applications are included in this DSP core. Moreover, key parameters of the DSP core are identified and analyzed to show their effects on performance index such as execution cycle, hardware gate count and power consumption. The parameters of the DSP core and the special functions required can be specified by user which is required by the application. The DSP core which generated by the generator is synthesizable and flexible RTL code for system integration. The turn around time of design process can be dramatically decreased. Furthermore, the generator can automatically optimize the structure of DSP core for different parameters. The design examples show that the variety of selection in implementation by using this parameterized generator and its flow provides the system designer to obtain better result in area, speed and power trade-off.",

author = "Tsao, {Ya Lan} and Lin, {Yu Chun} and Chen, {Wei Hao} and Huang, {Bo Shiang} and Shyh-Jye Jou",

year = "2004",

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doi = "10.1109/APCCAS.2004.1412770",

language = "English",

pages = "361--364",

note = "2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology ; Conference date: 06-12-2004 Through 09-12-2004",

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AU - Tsao, Ya Lan

AU - Lin, Yu Chun

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AU - Huang, Bo Shiang

AU - Jou, Shyh-Jye

PY - 2004/12

Y1 - 2004/12

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AB - In this paper, a parameterized module generator of DSP core for embedded application is proposed. Some special functions for the communication applications are included in this DSP core. Moreover, key parameters of the DSP core are identified and analyzed to show their effects on performance index such as execution cycle, hardware gate count and power consumption. The parameters of the DSP core and the special functions required can be specified by user which is required by the application. The DSP core which generated by the generator is synthesizable and flexible RTL code for system integration. The turn around time of design process can be dramatically decreased. Furthermore, the generator can automatically optimize the structure of DSP core for different parameters. The design examples show that the variety of selection in implementation by using this parameterized generator and its flow provides the system designer to obtain better result in area, speed and power trade-off.

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A module generator for parameterized DSP core

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