A Millimeter-Wave Frequency Synthesizer for 60 GHz Wireless Interconnect

Yong Yu Lin; Fan Ta Chen; Wei-Zen Chen

doi:10.1109/VLSI-DAT49148.2020.9196262

A Millimeter-Wave Frequency Synthesizer for 60 GHz Wireless Interconnect

Yong Yu Lin, Fan Ta Chen, Wei-Zen Chen

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

A millimeter-wave (mmW) frequency synthesizer for 60GHz wireless transceiver is presented. To achieve wide range and low noise operation, a new sampling PD based PLL (S-PLL) is proposed. In contrast to conventional sub-sampling PD based PLLs, it provides a wider capture range without suffering from harmonic lock problems. Also, compared to conventional CP-based PLLs, the inband noise is improved by 13 dB while the reference spur is improved by more than 16 dB. Implemented in TSMC 28nm CMOS technology, the core circuit occupies a chip area of 0.175mm2. The measured phase noise from a 48 GHz carrier is-95.7dBc/Hz at 1MHz offset. The power consumption is 54mW.

Original language	English
Title of host publication	2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Number of pages	2
ISBN (Electronic)	9781728160832
DOIs	https://doi.org/10.1109/VLSI-DAT49148.2020.9196262
State	Published - Aug 2020
Event	2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020 - Hsinchu, Taiwan Duration: 10 Aug 2020 → 13 Aug 2020

Publication series

Name	2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020

Conference

Conference	2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020
Country/Territory	Taiwan
City	Hsinchu
Period	10/08/20 → 13/08/20

Keywords

Charge Pump Phase-locked Loop (CP-PLL)
Sampling-PD PLL (S-PLL).
Sub-Sampling-PD PLL (SSPLL)

Access to Document

10.1109/VLSI-DAT49148.2020.9196262

Cite this

Lin, Y. Y., Chen, F. T., & Chen, W.-Z. (2020). A Millimeter-Wave Frequency Synthesizer for 60 GHz Wireless Interconnect. In 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020 Article 9196262 (2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT49148.2020.9196262

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title = "A Millimeter-Wave Frequency Synthesizer for 60 GHz Wireless Interconnect",

abstract = "A millimeter-wave (mmW) frequency synthesizer for 60GHz wireless transceiver is presented. To achieve wide range and low noise operation, a new sampling PD based PLL (S-PLL) is proposed. In contrast to conventional sub-sampling PD based PLLs, it provides a wider capture range without suffering from harmonic lock problems. Also, compared to conventional CP-based PLLs, the inband noise is improved by 13 dB while the reference spur is improved by more than 16 dB. Implemented in TSMC 28nm CMOS technology, the core circuit occupies a chip area of 0.175mm2. The measured phase noise from a 48 GHz carrier is-95.7dBc/Hz at 1MHz offset. The power consumption is 54mW. ",

keywords = "Charge Pump Phase-locked Loop (CP-PLL), Sampling-PD PLL (S-PLL)., Sub-Sampling-PD PLL (SSPLL)",

author = "Lin, {Yong Yu} and Chen, {Fan Ta} and Wei-Zen Chen",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020 ; Conference date: 10-08-2020 Through 13-08-2020",

year = "2020",

month = aug,

doi = "10.1109/VLSI-DAT49148.2020.9196262",

language = "English",

series = "2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020",

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Lin, YY, Chen, FT & Chen, W-Z 2020, A Millimeter-Wave Frequency Synthesizer for 60 GHz Wireless Interconnect. in 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020., 9196262, 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020, Institute of Electrical and Electronics Engineers Inc., 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020, Hsinchu, Taiwan, 10/08/20. https://doi.org/10.1109/VLSI-DAT49148.2020.9196262

A Millimeter-Wave Frequency Synthesizer for 60 GHz Wireless Interconnect. / Lin, Yong Yu; Chen, Fan Ta; Chen, Wei-Zen.
2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020. Institute of Electrical and Electronics Engineers Inc., 2020. 9196262 (2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - A millimeter-wave (mmW) frequency synthesizer for 60GHz wireless transceiver is presented. To achieve wide range and low noise operation, a new sampling PD based PLL (S-PLL) is proposed. In contrast to conventional sub-sampling PD based PLLs, it provides a wider capture range without suffering from harmonic lock problems. Also, compared to conventional CP-based PLLs, the inband noise is improved by 13 dB while the reference spur is improved by more than 16 dB. Implemented in TSMC 28nm CMOS technology, the core circuit occupies a chip area of 0.175mm2. The measured phase noise from a 48 GHz carrier is-95.7dBc/Hz at 1MHz offset. The power consumption is 54mW.

AB - A millimeter-wave (mmW) frequency synthesizer for 60GHz wireless transceiver is presented. To achieve wide range and low noise operation, a new sampling PD based PLL (S-PLL) is proposed. In contrast to conventional sub-sampling PD based PLLs, it provides a wider capture range without suffering from harmonic lock problems. Also, compared to conventional CP-based PLLs, the inband noise is improved by 13 dB while the reference spur is improved by more than 16 dB. Implemented in TSMC 28nm CMOS technology, the core circuit occupies a chip area of 0.175mm2. The measured phase noise from a 48 GHz carrier is-95.7dBc/Hz at 1MHz offset. The power consumption is 54mW.

KW - Charge Pump Phase-locked Loop (CP-PLL)

KW - Sampling-PD PLL (S-PLL).

KW - Sub-Sampling-PD PLL (SSPLL)

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M3 - Conference contribution

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BT - 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020

PB - Institute of Electrical and Electronics Engineers Inc.

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Lin YY, Chen FT, Chen WZ. A Millimeter-Wave Frequency Synthesizer for 60 GHz Wireless Interconnect. In 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020. Institute of Electrical and Electronics Engineers Inc. 2020. 9196262. (2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020). doi: 10.1109/VLSI-DAT49148.2020.9196262

A Millimeter-Wave Frequency Synthesizer for 60 GHz Wireless Interconnect

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