A low supply noise content-sensitive ROM architecture for SoC

Meng Fan Chang; Lih Yih Chiou; Kuei-Ann Wen

doi:10.1109/APCCAS.2004.1413056

A low supply noise content-sensitive ROM architecture for SoC

Meng Fan Chang^*, Lih Yih Chiou, Kuei-Ann Wen

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

3 Scopus citations

Abstract

Supply noise caused by fluctuation of peak current is increasingly important for SoC. This work proposes a content-sensitive architecture to effectively reduce the fluctuation of peak current and lower power consumption of ROMs for various code-patterns and cycles. We achieve both by arranging the data patterns of ROM and by adjusting the bitline structures accordingly. Our experiments on 0.25μm 256K bits ROM macros have shown that the fluctuation of peak current and power consumptions are less than 1.02% of the value using conventional approaches.

Original language	English
Pages	1021-1024
Number of pages	4
DOIs	https://doi.org/10.1109/APCCAS.2004.1413056
State	Published - Dec 2004
Event	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan Duration: 6 Dec 2004 → 9 Dec 2004

Conference

Conference	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
Country/Territory	Taiwan
City	Tainan
Period	6/12/04 → 9/12/04

Access to Document

10.1109/APCCAS.2004.1413056

Cite this

@conference{153143461e454ac78b356376b4eb66ba,

title = "A low supply noise content-sensitive ROM architecture for SoC",

abstract = "Supply noise caused by fluctuation of peak current is increasingly important for SoC. This work proposes a content-sensitive architecture to effectively reduce the fluctuation of peak current and lower power consumption of ROMs for various code-patterns and cycles. We achieve both by arranging the data patterns of ROM and by adjusting the bitline structures accordingly. Our experiments on 0.25μm 256K bits ROM macros have shown that the fluctuation of peak current and power consumptions are less than 1.02% of the value using conventional approaches.",

author = "Chang, {Meng Fan} and Chiou, {Lih Yih} and Kuei-Ann Wen",

year = "2004",

month = dec,

doi = "10.1109/APCCAS.2004.1413056",

language = "English",

pages = "1021--1024",

note = "2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology ; Conference date: 06-12-2004 Through 09-12-2004",

}

TY - CONF

T1 - A low supply noise content-sensitive ROM architecture for SoC

AU - Chang, Meng Fan

AU - Chiou, Lih Yih

AU - Wen, Kuei-Ann

PY - 2004/12

Y1 - 2004/12

N2 - Supply noise caused by fluctuation of peak current is increasingly important for SoC. This work proposes a content-sensitive architecture to effectively reduce the fluctuation of peak current and lower power consumption of ROMs for various code-patterns and cycles. We achieve both by arranging the data patterns of ROM and by adjusting the bitline structures accordingly. Our experiments on 0.25μm 256K bits ROM macros have shown that the fluctuation of peak current and power consumptions are less than 1.02% of the value using conventional approaches.

AB - Supply noise caused by fluctuation of peak current is increasingly important for SoC. This work proposes a content-sensitive architecture to effectively reduce the fluctuation of peak current and lower power consumption of ROMs for various code-patterns and cycles. We achieve both by arranging the data patterns of ROM and by adjusting the bitline structures accordingly. Our experiments on 0.25μm 256K bits ROM macros have shown that the fluctuation of peak current and power consumptions are less than 1.02% of the value using conventional approaches.

UR - http://www.scopus.com/inward/record.url?scp=13444287976&partnerID=8YFLogxK

U2 - 10.1109/APCCAS.2004.1413056

DO - 10.1109/APCCAS.2004.1413056

M3 - Paper

AN - SCOPUS:13444287976

SP - 1021

EP - 1024

T2 - 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology

Y2 - 6 December 2004 through 9 December 2004

ER -

A low supply noise content-sensitive ROM architecture for SoC

Abstract

Conference

Access to Document

Other files and links

Fingerprint

Cite this