A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique

Xin Ru Lee; Hsie-Chia Chang; Chen-Yi Lee

doi:10.1109/APCCAS.2010.5774991

A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique

Xin Ru Lee^*, Hsie-Chia Chang, Chen-Yi Lee

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

With a Viterbi decoder, the bit error probability of a communication system can be reduced. However, the power consumption of exploiting Viterbi decoder is an overhead to systems. In the Viterbi decoder, the survivor memory unit (SMU) is the most power critical due to data exchanging. A low-power radix-4 Viterbi decoder based on a differential cascode voltage switch with pass gate (DCVSPG) pulsed latch with sharing technique is proposed to process two bits concurrently. The dynamic power of SMU is reduced by the sharing technique. Moreover, the smaller clock loading also leads to power-efficient characteristic. Based on UMC 90nm process, the simulation results show the proposed Viterbi decoder with sharing technique could achieve better power scheme with energy efficiency 0.128 nJ/bit at 0.9V.

Original language	English
Title of host publication	Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Pages	1203-1206
Number of pages	4
DOIs	https://doi.org/10.1109/APCCAS.2010.5774991
State	Published - 1 Dec 2010
Event	2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur, Malaysia Duration: 6 Dec 2010 → 9 Dec 2010

Publication series

Name	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

Conference	2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Country/Territory	Malaysia
City	Kuala Lumpur
Period	6/12/10 → 9/12/10

Keywords

DCVSPG
pulsed latch
Viterbi decoder

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/APCCAS.2010.5774991

Cite this

Lee, X. R., Chang, H.-C., & Lee, C.-Y. (2010). A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique. In Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 (pp. 1203-1206). Article 5774991 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2010.5774991

@inproceedings{4db537188ac742a49ed12f182c2d0ee8,

title = "A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique",

abstract = "With a Viterbi decoder, the bit error probability of a communication system can be reduced. However, the power consumption of exploiting Viterbi decoder is an overhead to systems. In the Viterbi decoder, the survivor memory unit (SMU) is the most power critical due to data exchanging. A low-power radix-4 Viterbi decoder based on a differential cascode voltage switch with pass gate (DCVSPG) pulsed latch with sharing technique is proposed to process two bits concurrently. The dynamic power of SMU is reduced by the sharing technique. Moreover, the smaller clock loading also leads to power-efficient characteristic. Based on UMC 90nm process, the simulation results show the proposed Viterbi decoder with sharing technique could achieve better power scheme with energy efficiency 0.128 nJ/bit at 0.9V.",

keywords = "DCVSPG, pulsed latch, Viterbi decoder",

author = "Lee, {Xin Ru} and Hsie-Chia Chang and Chen-Yi Lee",

year = "2010",

month = dec,

day = "1",

doi = "10.1109/APCCAS.2010.5774991",

language = "English",

isbn = "9781424474561",

series = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",

pages = "1203--1206",

booktitle = "Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010",

note = "2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 ; Conference date: 06-12-2010 Through 09-12-2010",

}

Lee, XR, Chang, H-C & Lee, C-Y 2010, A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique. in Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010., 5774991, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, pp. 1203-1206, 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010, Kuala Lumpur, Malaysia, 6/12/10. https://doi.org/10.1109/APCCAS.2010.5774991

A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique. / Lee, Xin Ru; Chang, Hsie-Chia ; Lee, Chen-Yi.
Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010. 2010. p. 1203-1206 5774991 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique

AU - Lee, Xin Ru

AU - Chang, Hsie-Chia

AU - Lee, Chen-Yi

PY - 2010/12/1

Y1 - 2010/12/1

N2 - With a Viterbi decoder, the bit error probability of a communication system can be reduced. However, the power consumption of exploiting Viterbi decoder is an overhead to systems. In the Viterbi decoder, the survivor memory unit (SMU) is the most power critical due to data exchanging. A low-power radix-4 Viterbi decoder based on a differential cascode voltage switch with pass gate (DCVSPG) pulsed latch with sharing technique is proposed to process two bits concurrently. The dynamic power of SMU is reduced by the sharing technique. Moreover, the smaller clock loading also leads to power-efficient characteristic. Based on UMC 90nm process, the simulation results show the proposed Viterbi decoder with sharing technique could achieve better power scheme with energy efficiency 0.128 nJ/bit at 0.9V.

AB - With a Viterbi decoder, the bit error probability of a communication system can be reduced. However, the power consumption of exploiting Viterbi decoder is an overhead to systems. In the Viterbi decoder, the survivor memory unit (SMU) is the most power critical due to data exchanging. A low-power radix-4 Viterbi decoder based on a differential cascode voltage switch with pass gate (DCVSPG) pulsed latch with sharing technique is proposed to process two bits concurrently. The dynamic power of SMU is reduced by the sharing technique. Moreover, the smaller clock loading also leads to power-efficient characteristic. Based on UMC 90nm process, the simulation results show the proposed Viterbi decoder with sharing technique could achieve better power scheme with energy efficiency 0.128 nJ/bit at 0.9V.

KW - DCVSPG

KW - pulsed latch

KW - Viterbi decoder

UR - http://www.scopus.com/inward/record.url?scp=79959187509&partnerID=8YFLogxK

U2 - 10.1109/APCCAS.2010.5774991

DO - 10.1109/APCCAS.2010.5774991

M3 - Conference contribution

AN - SCOPUS:79959187509

SN - 9781424474561

T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

SP - 1203

EP - 1206

BT - Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010

T2 - 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010

Y2 - 6 December 2010 through 9 December 2010

ER -

A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique

Abstract

Publication series

Conference

Keywords

UN SDGs

Access to Document

Other files and links

Fingerprint

Cite this