A Low-power motion compensation IP core design for MPEG-1/2/4 video decoding

Chien Chih-Da; Chen Ho-Chun; Huang Lin-Chieh; Jiun-In Guo

doi:10.1109/ISCAS.2005.1465642

A Low-power motion compensation IP core design for MPEG-1/2/4 video decoding

Chien Chih-Da, Chen Ho-Chun^*, Huang Lin-Chieh, Jiun-In Guo

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Conference article › peer-review

8 Scopus citations

Abstract

This paper presents a low-power motion compensation IP core design for the MPEG-1/2/4 video decoding. The proposed design exploits the adder-based quarter-pixel filter optimized by data sharing for low cost consideration. This optimization reduces over 87 % hardware complexity as compared to the quarter-pixel filter in the existing design [4]. In addition, we propose a low-power design technique called dynamic partially guarded computation (DPGC) to reduce the power consumption on the pixel interpolation. After applying the DPGC, we can reduce the 60% power consumption of interpolation operations in the proposed design. Using a 0.18μm CMOS technology, the proposed design achieves real-time processing of MPEG-1/2/4 decoding on 4CIF video when operated at 54MHz. In addition, the proposed design has been integrated into a MPEG-4 video decoder for system verification through XILINX multimedia FPGA board.

Original language	English
Article number	1465642
Pages (from-to)	4542-4545
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2005.1465642
State	Published - 1 Dec 2005
Event	IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: 23 May 2005 → 26 May 2005

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title = "A Low-power motion compensation IP core design for MPEG-1/2/4 video decoding",

abstract = "This paper presents a low-power motion compensation IP core design for the MPEG-1/2/4 video decoding. The proposed design exploits the adder-based quarter-pixel filter optimized by data sharing for low cost consideration. This optimization reduces over 87 \% hardware complexity as compared to the quarter-pixel filter in the existing design [4]. In addition, we propose a low-power design technique called dynamic partially guarded computation (DPGC) to reduce the power consumption on the pixel interpolation. After applying the DPGC, we can reduce the 60\% power consumption of interpolation operations in the proposed design. Using a 0.18μm CMOS technology, the proposed design achieves real-time processing of MPEG-1/2/4 decoding on 4CIF video when operated at 54MHz. In addition, the proposed design has been integrated into a MPEG-4 video decoder for system verification through XILINX multimedia FPGA board.",

author = "Chien Chih-Da and Chen Ho-Chun and Huang Lin-Chieh and Jiun-In Guo",

year = "2005",

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doi = "10.1109/ISCAS.2005.1465642",

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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

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note = "IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 ; Conference date: 23-05-2005 Through 26-05-2005",

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T1 - A Low-power motion compensation IP core design for MPEG-1/2/4 video decoding

AU - Chih-Da, Chien

AU - Ho-Chun, Chen

AU - Lin-Chieh, Huang

AU - Guo, Jiun-In

PY - 2005/12/1

Y1 - 2005/12/1

N2 - This paper presents a low-power motion compensation IP core design for the MPEG-1/2/4 video decoding. The proposed design exploits the adder-based quarter-pixel filter optimized by data sharing for low cost consideration. This optimization reduces over 87 % hardware complexity as compared to the quarter-pixel filter in the existing design [4]. In addition, we propose a low-power design technique called dynamic partially guarded computation (DPGC) to reduce the power consumption on the pixel interpolation. After applying the DPGC, we can reduce the 60% power consumption of interpolation operations in the proposed design. Using a 0.18μm CMOS technology, the proposed design achieves real-time processing of MPEG-1/2/4 decoding on 4CIF video when operated at 54MHz. In addition, the proposed design has been integrated into a MPEG-4 video decoder for system verification through XILINX multimedia FPGA board.

AB - This paper presents a low-power motion compensation IP core design for the MPEG-1/2/4 video decoding. The proposed design exploits the adder-based quarter-pixel filter optimized by data sharing for low cost consideration. This optimization reduces over 87 % hardware complexity as compared to the quarter-pixel filter in the existing design [4]. In addition, we propose a low-power design technique called dynamic partially guarded computation (DPGC) to reduce the power consumption on the pixel interpolation. After applying the DPGC, we can reduce the 60% power consumption of interpolation operations in the proposed design. Using a 0.18μm CMOS technology, the proposed design achieves real-time processing of MPEG-1/2/4 decoding on 4CIF video when operated at 54MHz. In addition, the proposed design has been integrated into a MPEG-4 video decoder for system verification through XILINX multimedia FPGA board.

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DO - 10.1109/ISCAS.2005.1465642

M3 - Conference article

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JO - Proceedings - IEEE International Symposium on Circuits and Systems

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T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005

Y2 - 23 May 2005 through 26 May 2005

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A Low-power motion compensation IP core design for MPEG-1/2/4 video decoding

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