A low-power level-converting double-edge-triggered flip-flop design

Li Rong Wang, Kai Yu Lo, Shyh-Jye Jou

    Research output: Contribution to journalArticlepeer-review


    This paper proposes a new double-edge-triggered implicitly level-converting flip-flop, suitable for a low-power and low-voltage design. The design employs a sense amplifier architecture to reduce the delay and power consumption. Experimentally, when implemented with a 130-nm, single-Vt and 0.84V VDD process, it achieves 64% power-delay product (PDP) improvement, and moreover, 78% PDP improvement when implemented with a mixed-Vt technology, as compared to that of the classic double-edge-triggered flip-flop design.

    Original languageEnglish
    Pages (from-to)1351-1355
    Number of pages5
    JournalIEICE Transactions on Electronics
    Issue number10
    StatePublished - 1 Jan 2013


    • Double-edge-triggered
    • Flip-flop
    • Level-converting
    • Mixed threshold voltage
    • Sense amplifier


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