A low power independent component analysis processor in 90nm CMOS technology for portable EEG signal processing systems

Chiu Kuo Chen, Yi Yuan Wang, Zong Han Hsieh, Ericson Chua, Wai-Chi  Fang*, Tzyy Ping Jung

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    5 Scopus citations

    Abstract

    This paper presents a low-power VLSI implementation of a 4-channel independent component analysis (ICA) processor for portable EEG signal processing applications. The low-power scheme employed for this ICA chip is based on power gating and clock gating by utilizing Cadence common power flow (CPF) low-power methodology and also according to the characteristics of ICA training behavior using different training window sizes. The proposed low power ICA processor can separate EEG and mixed EEG-like super-Gaussian signals in real time. The chip can be operated at up to 60MHz working frequency and a maximum sampling rate of 9.394 KHz for EEG signals. The power consumption of this chip is 0.690 mW during training under the condition of 0.9V supply voltage and 10 MHz operating frequency using UMC 90nm High-Vt CMOS technology. The total chip area is 1230 1230 m2.

    Original languageEnglish
    Title of host publication2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
    Pages801-804
    Number of pages4
    DOIs
    StatePublished - 2 Aug 2011
    Event2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 - Rio de Janeiro, Brazil
    Duration: 15 May 201118 May 2011

    Publication series

    NameProceedings - IEEE International Symposium on Circuits and Systems
    ISSN (Print)0271-4310

    Conference

    Conference2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
    Country/TerritoryBrazil
    CityRio de Janeiro
    Period15/05/1118/05/11

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