A low power hearing aid computing platform using lightweight processing elements

Kuo Chiang Chang; Yu Wen Chen; Yu Ting Kuo; Chih-Wei Liu

doi:10.1109/ISCAS.2012.6271888

A low power hearing aid computing platform using lightweight processing elements

Kuo Chiang Chang^*, Yu Wen Chen, Yu Ting Kuo, Chih-Wei Liu

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

10 Scopus citations

Abstract

This paper presents a power-efficient computing platform for hearing aids. The proposed platform composes four heterogeneous processing elements. Each processing element includes one tiny RISC processor and several power-efficient hardwired accelerators. The hardwired accelerators integrate static floating-point and truncated multiplier to improve signal-to-noise ratio and reduce computational complexity. Compared to the post-truncate multiplication in FIR filter, the proposed static floating-point datapath reduces 50.8% area and improves 2.2 dB SNR simultaneously.

Original language	English
Pages	2785-2788
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2012.6271888
State	Published - 2012
Event	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Duration: 20 May 2012 → 23 May 2012

Conference

Conference	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/Territory	Korea, Republic of
City	Seoul
Period	20/05/12 → 23/05/12

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/ISCAS.2012.6271888

Cite this

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abstract = "This paper presents a power-efficient computing platform for hearing aids. The proposed platform composes four heterogeneous processing elements. Each processing element includes one tiny RISC processor and several power-efficient hardwired accelerators. The hardwired accelerators integrate static floating-point and truncated multiplier to improve signal-to-noise ratio and reduce computational complexity. Compared to the post-truncate multiplication in FIR filter, the proposed static floating-point datapath reduces 50.8% area and improves 2.2 dB SNR simultaneously.",

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AB - This paper presents a power-efficient computing platform for hearing aids. The proposed platform composes four heterogeneous processing elements. Each processing element includes one tiny RISC processor and several power-efficient hardwired accelerators. The hardwired accelerators integrate static floating-point and truncated multiplier to improve signal-to-noise ratio and reduce computational complexity. Compared to the post-truncate multiplication in FIR filter, the proposed static floating-point datapath reduces 50.8% area and improves 2.2 dB SNR simultaneously.

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A low power hearing aid computing platform using lightweight processing elements

Abstract

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UN SDGs

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