TY - JOUR
T1 - A low-power, differential relaxation oscillator with the self-threshold-tracking and swing-boosting techniques in 0.18-μm CMOS
AU - Lu, Shao Yung
AU - Liao, Yu-Te
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2019/2
Y1 - 2019/2
N2 - This paper presents a fully integrated, 8.2-MHz relaxation oscillator with a self-threshold-tracking loop and swing-boosting technique for improving its long-term frequency stability and noise performance. The proposed latch-based relaxation oscillator increases the transition speed to reduce the static power consumption. To decrease the process-voltageerature dependence, we propose a self-threshold-tracking loop to ensure that the transition point of the inverter-based comparator is set to a fixed ratio of the supply voltage. In addition, the comparator delay can be compensated by the tracking loop, relaxing the requirements of comparator power consumption. The design is implemented in a 0.18-μm CMOS process. The design achieves a period jitter of 7.66 psrms, the phase noise of-109 dBc/Hz at an offset frequency of 100 kHz, and an Allan deviation noise floor of 1.56 ppm. The resultant figure of merit is 160.8 dBc/Hz, while only consuming 46.3 μW. The power efficiency of the design is 5.6 kHz/nW. As for the supply sensitivity, the design achieves 0.9 %/0.1 V, which is 10 × lower than the design with no compensation loop. The measured temperature coefficient of the proposed oscillators is 123 ppm/°C from-20 °C to 100 °C without any trimming process.
AB - This paper presents a fully integrated, 8.2-MHz relaxation oscillator with a self-threshold-tracking loop and swing-boosting technique for improving its long-term frequency stability and noise performance. The proposed latch-based relaxation oscillator increases the transition speed to reduce the static power consumption. To decrease the process-voltageerature dependence, we propose a self-threshold-tracking loop to ensure that the transition point of the inverter-based comparator is set to a fixed ratio of the supply voltage. In addition, the comparator delay can be compensated by the tracking loop, relaxing the requirements of comparator power consumption. The design is implemented in a 0.18-μm CMOS process. The design achieves a period jitter of 7.66 psrms, the phase noise of-109 dBc/Hz at an offset frequency of 100 kHz, and an Allan deviation noise floor of 1.56 ppm. The resultant figure of merit is 160.8 dBc/Hz, while only consuming 46.3 μW. The power efficiency of the design is 5.6 kHz/nW. As for the supply sensitivity, the design achieves 0.9 %/0.1 V, which is 10 × lower than the design with no compensation loop. The measured temperature coefficient of the proposed oscillators is 123 ppm/°C from-20 °C to 100 °C without any trimming process.
KW - CMOS
KW - low power
KW - relaxation oscillator
KW - self-threshold-tracking loop
KW - swing boosting
UR - http://www.scopus.com/inward/record.url?scp=85058136835&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2018.2877927
DO - 10.1109/JSSC.2018.2877927
M3 - Article
AN - SCOPUS:85058136835
SN - 0018-9200
VL - 54
SP - 392
EP - 402
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 2
M1 - 8558702
ER -