A low-power CMOS Voltage Reference Circuit based on subthreshold operation

Chia Wei Chang; Tien Yu Lo; Chia Min Chen; Kuo Hsi Wu; Chung-Chih Hung

doi:10.1109/ISCAS.2007.377877

A low-power CMOS Voltage Reference Circuit based on subthreshold operation

Chia Wei Chang^*, Tien Yu Lo, Chia Min Chen, Kuo Hsi Wu, Chung-Chih Hung

^*Corresponding author for this work

Department of Electrical and Computer Engineering

Research output: Contribution to journal › Conference article › peer-review

16 Scopus citations

Abstract

A low power CMOS Voltage Reference Circuit was designed and implemented by TSMC 0.18-μm CMOS process. The voltage reference circuit uses the V _GS difference between two MOSFETs operating in the weak-inversion region to generate the voltage with positive temperature coefficient The reference voltage can be obtained by combining the weighted V _GS difference with weak-inversion V _GS voltage, which has a negative temperature coefficient. This circuit provides a nominal reference voltage of 621 mV, a temperature coefficient of 11.5 ppm/°C in [-20°C-120°C] from a 1.5 V supply voltage. The line regulation of the reference voltage is 6 mV/V when the supply voltage is increased from 1.5 V to 3 V. The chip area is 0.132 mm ² and dissipates 17.25 μW at room temperature. By connecting a 0.22 pF loading capacitor, the measured noise density at 100 Hz and 100 kHz is 0.14 μV/√Hz and 22.2 μV/√Hz, respectively.

Original language	American English
Article number	4253520
Pages (from-to)	3844-3847
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2007.377877
State	Published - 27 Sep 2007
Event	2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States Duration: 27 May 2007 → 30 May 2007

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title = "A low-power CMOS Voltage Reference Circuit based on subthreshold operation",

abstract = " A low power CMOS Voltage Reference Circuit was designed and implemented by TSMC 0.18-μm CMOS process. The voltage reference circuit uses the V GS difference between two MOSFETs operating in the weak-inversion region to generate the voltage with positive temperature coefficient The reference voltage can be obtained by combining the weighted V GS difference with weak-inversion V GS voltage, which has a negative temperature coefficient. This circuit provides a nominal reference voltage of 621 mV, a temperature coefficient of 11.5 ppm/°C in [-20°C-120°C] from a 1.5 V supply voltage. The line regulation of the reference voltage is 6 mV/V when the supply voltage is increased from 1.5 V to 3 V. The chip area is 0.132 mm 2 and dissipates 17.25 μW at room temperature. By connecting a 0.22 pF loading capacitor, the measured noise density at 100 Hz and 100 kHz is 0.14 μV/√Hz and 22.2 μV/√Hz, respectively.",

author = "Chang, {Chia Wei} and Lo, {Tien Yu} and Chen, {Chia Min} and Wu, {Kuo Hsi} and Chung-Chih Hung",

year = "2007",

month = sep,

day = "27",

doi = "10.1109/ISCAS.2007.377877",

language = "American English",

pages = "3844--3847",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 ; Conference date: 27-05-2007 Through 30-05-2007",

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TY - JOUR

T1 - A low-power CMOS Voltage Reference Circuit based on subthreshold operation

AU - Chang, Chia Wei

AU - Lo, Tien Yu

AU - Chen, Chia Min

AU - Wu, Kuo Hsi

AU - Hung, Chung-Chih

PY - 2007/9/27

Y1 - 2007/9/27

N2 - A low power CMOS Voltage Reference Circuit was designed and implemented by TSMC 0.18-μm CMOS process. The voltage reference circuit uses the V GS difference between two MOSFETs operating in the weak-inversion region to generate the voltage with positive temperature coefficient The reference voltage can be obtained by combining the weighted V GS difference with weak-inversion V GS voltage, which has a negative temperature coefficient. This circuit provides a nominal reference voltage of 621 mV, a temperature coefficient of 11.5 ppm/°C in [-20°C-120°C] from a 1.5 V supply voltage. The line regulation of the reference voltage is 6 mV/V when the supply voltage is increased from 1.5 V to 3 V. The chip area is 0.132 mm 2 and dissipates 17.25 μW at room temperature. By connecting a 0.22 pF loading capacitor, the measured noise density at 100 Hz and 100 kHz is 0.14 μV/√Hz and 22.2 μV/√Hz, respectively.

AB - A low power CMOS Voltage Reference Circuit was designed and implemented by TSMC 0.18-μm CMOS process. The voltage reference circuit uses the V GS difference between two MOSFETs operating in the weak-inversion region to generate the voltage with positive temperature coefficient The reference voltage can be obtained by combining the weighted V GS difference with weak-inversion V GS voltage, which has a negative temperature coefficient. This circuit provides a nominal reference voltage of 621 mV, a temperature coefficient of 11.5 ppm/°C in [-20°C-120°C] from a 1.5 V supply voltage. The line regulation of the reference voltage is 6 mV/V when the supply voltage is increased from 1.5 V to 3 V. The chip area is 0.132 mm 2 and dissipates 17.25 μW at room temperature. By connecting a 0.22 pF loading capacitor, the measured noise density at 100 Hz and 100 kHz is 0.14 μV/√Hz and 22.2 μV/√Hz, respectively.

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U2 - 10.1109/ISCAS.2007.377877

DO - 10.1109/ISCAS.2007.377877

M3 - Conference article

AN - SCOPUS:34548823251

SN - 0271-4310

SP - 3844

EP - 3847

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

M1 - 4253520

T2 - 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007

Y2 - 27 May 2007 through 30 May 2007

ER -

A low-power CMOS Voltage Reference Circuit based on subthreshold operation

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