A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology

In this paper, we propose an architecture for low power SRAM designs by using hierarchical bitlines for SRAM macros with the charge sharing Read technique. Moreover, sense amplifiers are important circuits for accessing the data from internal storage nodes to data outputs. We compare two types of sense amplifiers, a current-latched sense amplifier (CLSA) and a voltage-latched sense amplifier (VLSA), and focus on the characteristics of input offset voltages and power consumption in 28 nm HPM CMOS technology. Detailed post-layout simulations with Monte Carlo mismatch model are utilized to compare the two structures. From our analysis and implementation results, using the pass-gate based hierarchical bitline with the charge sharing Read scheme gains at least 59% and 66% LBL/GBL power reduction for a 2-bank and a 4-bank hierarchical architectures at five corners, respectively. VLSA performs lower input offset voltage, higher speed and lower power consumption as compared to CLSA. The proposed combination of the pass-gate based hierarchical bitline with the charge sharing Read scheme and VLSA is suitable for SRAM macros with the high-speed and low-power design considerations.