A low power 2.4/5.2GHz concurrent receiver using current-reused architecture

Keyphrases

• Noise Figure 100%
• Low Power 100%
• P1dB 100%
• Maximum Gain 100%
• Current Reuse 100%
• Receiver Design 50%
• CMOS Process 50%
• Total Energy Consumption 50%
• Supply Voltage 50%
• Chip Area 50%
• RF Front-end 50%
• Mixer 50%
• Energy Consumption Reduction 50%
• 1-dB Compression Point 50%
• Low Noise Amplifier 50%
• Impedance Matching Network 50%
• Gain Stage 50%
• Prototype chip 50%
• Concurrent Dual-band 50%
• Front-end Design 50%
• Current Reuse Technique 50%
• Variable Gain 50%
• Baseband Amplifier 50%
• 2.4 GHz ISM Band 50%
• Wireless Sensing Application 50%

Engineering

• Noise Figure 100%
• Electric Power Utilization 100%
• Supply Voltage 50%
• Amplifier 50%
• Sensing Application 50%
• Front End 50%
• Chip Area 50%
• Mixers (Machinery) 50%
• Db Compression Point 50%
• Low Noise Amplifier 50%
• Matching Network 50%
• Gain Stage 50%