A low-power 2.4-GHz CMOS GFSK transceiver with a digital demodulator using time-to-digital conversion

Chia Pei Chen, Ming Jen Yang, Hsun Hsiu Huang, Tung Ying Chiang, Jheng Liang Chen, Ming Chieh Chen, Kuei-Ann Wen

Research output: Contribution to journalArticlepeer-review

27 Scopus citations


A technique of time-to-digital conversion is utilized in a digital demodulator for a low-power 2.4-GHz CMOS GFSK transceiver. The proposed time-to-digital converter (TDC) employs a self-sampling technique and an auto-calibration algorithm to avoid edge synchronization problems and the need of a delay-locked loop (DLL). With the TDC, a limiter and a digital demodulator can be employed simultaneously in the receiver to achieve low power consumption and high performance. Additionally, in the transmitter, the open-loop VCO modulation is adopted to save hardware and power consumption. The transmitter frequency drift in open-loop modulation and frequency offset between the receiver and the transmitter can be easily resolved by the proposed receiver architecture. All required building blocks of the proposed transceiver, except a RF matching network and a crystal, were implemented on a 4-mm2 chip by a 0.18-μm CMOS process. The receiver achieves -89-dBm sensitivity at 0.1% BER with 1-Mb/s data rate, and the transmitter delivers up to 0-dBm output power. The receiver and transmitter consume 13.3 mA and 10.7 mA, respectively, from a 1.8-V power supply.

Original languageEnglish
Pages (from-to)2738-2748
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number12
StatePublished - 1 Jan 2009


  • Complex bandpass filter
  • Demodulator
  • Frequency synthesizer
  • Low-noise amplifier (LNA)
  • Open-loop VCO modulation
  • Time-to-digital converter (TDC)


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