@inproceedings{152a1a3965ba47e49dc84891be0cdbf6,
title = "A low-jitter ADPLL with adaptive high-order loop filter and fine grain varactor based DCO",
abstract = "An all-digital phase-locked loop (ADPLL) with adaptive higher-order filter is proposed in this paper. The proposed ADPLL can select the first to third order of the loop filter by turning the IIR filter to adjust the system performance and attenuate input noise. Moreover, the phenomenon that spurious tone is getting closer to the main tone at higher-order ADPLL will be analyzed in this paper. The chip has been designed and implemented in TSMC 40 nm GP 1P10M CMOS process technology. The total area of the ADPLL core is 0.0106 mm2. By turning on the IIR filter, the measured rms jitter is 0.6 ps (0.298 % UI) and the power consumption is 5.1 mW from a 0.9 V supply at 4.96 GHz output frequency with 40 MHz reference clock.",
keywords = "All-digital phase-locked loop, Higher-order filter, Low jitter",
author = "Chang, {Chia Chen} and Chin, {Yu Tung} and Ibrahim, {Hossameldin A.} and Chang, {Kang Yu} and Jou, {Shyh Jye}",
note = "Publisher Copyright: {\textcopyright} 2021 IEEE; 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 ; Conference date: 22-05-2021 Through 28-05-2021",
year = "2021",
month = may,
day = "22",
doi = "10.1109/ISCAS51556.2021.9401328",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings",
address = "United States",
}