A Low-Error and Area-Time Efficient Fixed-Width Booth Multiplier

Min An Song; Lan Da Van; Ting Chun Huang; Sy Yen Kuo

doi:10.1109/MWSCAS.2003.1562355

A Low-Error and Area-Time Efficient Fixed-Width Booth Multiplier

Min An Song, Lan Da Van^*, Ting Chun Huang, Sy Yen Kuo

^*Corresponding author for this work

Institute of Computer Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

In this paper, we develop a new methodology for designing a lower-error and area-time efficient 2 s-complement fixed-width Booth multiplier that receives two n-bit numbers and produces an n-bit product. By properly choosing the generalized index and binary thresholding, we derive a better error-compensation bias to reduce the truncation error. Since the proposed error-compensation bias is realizable, the constructing low-error fixed-width Booth multiplier is area-time efficient for VLSI implementation. Finally, we successfully apply the proposed fixed-width Booth multiplier to speech signal processing. The simulation results show that the performance is superior to that using the direct-truncation fixed-width Booth multiplier.

Original language	English
Title of host publication	Midwest Symposium on Circuits and Systems
Editors	Nadder Hamdy
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	590-593
Number of pages	4
ISBN (Electronic)	0780382943
DOIs	https://doi.org/10.1109/MWSCAS.2003.1562355
State	Published - 2003
Event	46th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2003 - Cairo, Egypt Duration: 27 Dec 2003 → 30 Dec 2003

Publication series

Name	Midwest Symposium on Circuits and Systems
Volume	2
ISSN (Print)	1548-3746

Conference

Conference	46th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2003
Country/Territory	Egypt
City	Cairo
Period	27/12/03 → 30/12/03

Access to Document

10.1109/MWSCAS.2003.1562355

Cite this

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title = "A Low-Error and Area-Time Efficient Fixed-Width Booth Multiplier",

abstract = "In this paper, we develop a new methodology for designing a lower-error and area-time efficient 2 s-complement fixed-width Booth multiplier that receives two n-bit numbers and produces an n-bit product. By properly choosing the generalized index and binary thresholding, we derive a better error-compensation bias to reduce the truncation error. Since the proposed error-compensation bias is realizable, the constructing low-error fixed-width Booth multiplier is area-time efficient for VLSI implementation. Finally, we successfully apply the proposed fixed-width Booth multiplier to speech signal processing. The simulation results show that the performance is superior to that using the direct-truncation fixed-width Booth multiplier.",

author = "Song, {Min An} and Van, {Lan Da} and Huang, {Ting Chun} and Kuo, {Sy Yen}",

note = "Publisher Copyright: {\textcopyright} 2004 IEEE.; 46th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2003 ; Conference date: 27-12-2003 Through 30-12-2003",

year = "2003",

doi = "10.1109/MWSCAS.2003.1562355",

language = "English",

series = "Midwest Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "590--593",

editor = "Nadder Hamdy",

booktitle = "Midwest Symposium on Circuits and Systems",

address = "美國",

}

Song, MA, Van, LD, Huang, TC & Kuo, SY 2003, A Low-Error and Area-Time Efficient Fixed-Width Booth Multiplier. in N Hamdy (ed.), Midwest Symposium on Circuits and Systems. Midwest Symposium on Circuits and Systems, vol. 2, Institute of Electrical and Electronics Engineers Inc., pp. 590-593, 46th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2003, Cairo, Egypt, 27/12/03. https://doi.org/10.1109/MWSCAS.2003.1562355

A Low-Error and Area-Time Efficient Fixed-Width Booth Multiplier. / Song, Min An; Van, Lan Da; Huang, Ting Chun et al.
Midwest Symposium on Circuits and Systems. ed. / Nadder Hamdy. Institute of Electrical and Electronics Engineers Inc., 2003. p. 590-593 (Midwest Symposium on Circuits and Systems; Vol. 2).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A Low-Error and Area-Time Efficient Fixed-Width Booth Multiplier

AU - Song, Min An

AU - Van, Lan Da

AU - Huang, Ting Chun

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PY - 2003

Y1 - 2003

N2 - In this paper, we develop a new methodology for designing a lower-error and area-time efficient 2 s-complement fixed-width Booth multiplier that receives two n-bit numbers and produces an n-bit product. By properly choosing the generalized index and binary thresholding, we derive a better error-compensation bias to reduce the truncation error. Since the proposed error-compensation bias is realizable, the constructing low-error fixed-width Booth multiplier is area-time efficient for VLSI implementation. Finally, we successfully apply the proposed fixed-width Booth multiplier to speech signal processing. The simulation results show that the performance is superior to that using the direct-truncation fixed-width Booth multiplier.

AB - In this paper, we develop a new methodology for designing a lower-error and area-time efficient 2 s-complement fixed-width Booth multiplier that receives two n-bit numbers and produces an n-bit product. By properly choosing the generalized index and binary thresholding, we derive a better error-compensation bias to reduce the truncation error. Since the proposed error-compensation bias is realizable, the constructing low-error fixed-width Booth multiplier is area-time efficient for VLSI implementation. Finally, we successfully apply the proposed fixed-width Booth multiplier to speech signal processing. The simulation results show that the performance is superior to that using the direct-truncation fixed-width Booth multiplier.

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DO - 10.1109/MWSCAS.2003.1562355

M3 - Conference contribution

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T3 - Midwest Symposium on Circuits and Systems

SP - 590

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BT - Midwest Symposium on Circuits and Systems

A2 - Hamdy, Nadder

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 46th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2003

Y2 - 27 December 2003 through 30 December 2003

ER -

A Low-Error and Area-Time Efficient Fixed-Width Booth Multiplier

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