A long block length BCH decoder for DVB-S2 application

Yi Min Lin; Jau Yet Wu; Chien Ching Lin; Hsie-Chia Chang

A long block length BCH decoder for DVB-S2 application

Yi Min Lin^*, Jau Yet Wu, Chien Ching Lin, Hsie-Chia Chang

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Scopus citations

Abstract

In this paper, a low-complexity and full-mode BCH decoder with long block length for DVB-S2 application is presented. With the reversed error locator polynomial, our proposed reversed Berlekamp-Massey algorithm features a sharing architecture to perform parallel-4 syndrome and Chien search calculations. Concatenated with the LDPC decoder, which has a long decoding latency and a short period of data output time, the proposed parallel-4 BCH decoder ensures the sufficient throughput with only one bank memory. Moreover, a composite field divider instead of a large Galois field inversion table is also presented to reduce complexity. After implemented in 0.13μ m CMOS technology, our parallel-4 BCH decoder occupied 44K gate count can reach 380Mb/s according to the post-layout simulations.

Original language	English
Title of host publication	ISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings
Pages	171-174
Number of pages	4
State	Published - 14 Dec 2009
Event	12th International Symposium on Integrated Circuits, ISIC-2009 - Singapore, Singapore Duration: 14 Dec 2009 → 16 Dec 2009

Publication series

Name	ISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings

Conference

Conference	12th International Symposium on Integrated Circuits, ISIC-2009
Country/Territory	Singapore
City	Singapore
Period	14/12/09 → 16/12/09

Cite this

@inproceedings{4676f7670dba4f8cbde9e400cdd5f664,

title = "A long block length BCH decoder for DVB-S2 application",

abstract = "In this paper, a low-complexity and full-mode BCH decoder with long block length for DVB-S2 application is presented. With the reversed error locator polynomial, our proposed reversed Berlekamp-Massey algorithm features a sharing architecture to perform parallel-4 syndrome and Chien search calculations. Concatenated with the LDPC decoder, which has a long decoding latency and a short period of data output time, the proposed parallel-4 BCH decoder ensures the sufficient throughput with only one bank memory. Moreover, a composite field divider instead of a large Galois field inversion table is also presented to reduce complexity. After implemented in 0.13μ m CMOS technology, our parallel-4 BCH decoder occupied 44K gate count can reach 380Mb/s according to the post-layout simulations.",

author = "Lin, {Yi Min} and Wu, {Jau Yet} and Lin, {Chien Ching} and Hsie-Chia Chang",

year = "2009",

month = dec,

day = "14",

language = "English",

isbn = "9789810824686",

series = "ISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings",

pages = "171--174",

booktitle = "ISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings",

note = "12th International Symposium on Integrated Circuits, ISIC-2009 ; Conference date: 14-12-2009 Through 16-12-2009",

}

Lin, YM, Wu, JY, Lin, CC & Chang, H-C 2009, A long block length BCH decoder for DVB-S2 application. in ISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings., 5403893, ISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings, pp. 171-174, 12th International Symposium on Integrated Circuits, ISIC-2009, Singapore, Singapore, 14/12/09.

A long block length BCH decoder for DVB-S2 application. / Lin, Yi Min; Wu, Jau Yet; Lin, Chien Ching et al.
ISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings. 2009. p. 171-174 5403893 (ISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A long block length BCH decoder for DVB-S2 application

AU - Lin, Yi Min

AU - Wu, Jau Yet

AU - Lin, Chien Ching

AU - Chang, Hsie-Chia

PY - 2009/12/14

Y1 - 2009/12/14

N2 - In this paper, a low-complexity and full-mode BCH decoder with long block length for DVB-S2 application is presented. With the reversed error locator polynomial, our proposed reversed Berlekamp-Massey algorithm features a sharing architecture to perform parallel-4 syndrome and Chien search calculations. Concatenated with the LDPC decoder, which has a long decoding latency and a short period of data output time, the proposed parallel-4 BCH decoder ensures the sufficient throughput with only one bank memory. Moreover, a composite field divider instead of a large Galois field inversion table is also presented to reduce complexity. After implemented in 0.13μ m CMOS technology, our parallel-4 BCH decoder occupied 44K gate count can reach 380Mb/s according to the post-layout simulations.

AB - In this paper, a low-complexity and full-mode BCH decoder with long block length for DVB-S2 application is presented. With the reversed error locator polynomial, our proposed reversed Berlekamp-Massey algorithm features a sharing architecture to perform parallel-4 syndrome and Chien search calculations. Concatenated with the LDPC decoder, which has a long decoding latency and a short period of data output time, the proposed parallel-4 BCH decoder ensures the sufficient throughput with only one bank memory. Moreover, a composite field divider instead of a large Galois field inversion table is also presented to reduce complexity. After implemented in 0.13μ m CMOS technology, our parallel-4 BCH decoder occupied 44K gate count can reach 380Mb/s according to the post-layout simulations.

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M3 - Conference contribution

AN - SCOPUS:77950403758

SN - 9789810824686

T3 - ISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings

SP - 171

EP - 174

BT - ISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings

T2 - 12th International Symposium on Integrated Circuits, ISIC-2009

Y2 - 14 December 2009 through 16 December 2009

ER -

A long block length BCH decoder for DVB-S2 application

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