A lightweight 1.16 pJ/bit processor for the authenticated encryption scheme KetjeSR

Yun Wen Lu; Antoon Purnal; Simon Vandenhende; Chen Yi Lee; Ingrid Verbauwhede; Hsie Chia Chang

doi:10.1109/VLSI-DAT.2019.8741601

A lightweight 1.16 pJ/bit processor for the authenticated encryption scheme KetjeSR

Yun Wen Lu, Antoon Purnal, Simon Vandenhende, Chen Yi Lee, Ingrid Verbauwhede, Hsie Chia Chang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents the results of the first ASIC implementation of the authenticated encryption scheme KetjeSR. The design covers the encryption and decryption operation in combination with a handshake protocol for the data transfer. The chip implementation was done in a TSMC 90nm GUTM process. The encryption/decryption module has an area footprint of 12.2kGE. The processor reaches an end-to-end throughput of 2.08 Gbps when running at a clock frequency of 130 MHz. The design was further optimized for low power and consumes 2.421 mW. The optimization is based on the reuse of the permutation function in combination with extensive pipelining. In terms of energy, the encryption operation costs 1.16 pJ/bit.

Original language	English
Title of host publication	2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728106557
DOIs	https://doi.org/10.1109/VLSI-DAT.2019.8741601
State	Published - Apr 2019
Event	2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 - Hsinchu, Taiwan Duration: 22 Apr 2019 → 25 Apr 2019

Publication series

Name	2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

Conference

Conference	2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
Country/Territory	Taiwan
City	Hsinchu
Period	22/04/19 → 25/04/19

Access to Document

10.1109/VLSI-DAT.2019.8741601

Cite this

Lu, Y. W., Purnal, A., Vandenhende, S., Lee, C. Y., Verbauwhede, I., & Chang, H. C. (2019). A lightweight 1.16 pJ/bit processor for the authenticated encryption scheme KetjeSR. In 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 [8741601] (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2019.8741601

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title = "A lightweight 1.16 pJ/bit processor for the authenticated encryption scheme KetjeSR",

abstract = "This paper presents the results of the first ASIC implementation of the authenticated encryption scheme KetjeSR. The design covers the encryption and decryption operation in combination with a handshake protocol for the data transfer. The chip implementation was done in a TSMC 90nm GUTM process. The encryption/decryption module has an area footprint of 12.2kGE. The processor reaches an end-to-end throughput of 2.08 Gbps when running at a clock frequency of 130 MHz. The design was further optimized for low power and consumes 2.421 mW. The optimization is based on the reuse of the permutation function in combination with extensive pipelining. In terms of energy, the encryption operation costs 1.16 pJ/bit.",

author = "Lu, {Yun Wen} and Antoon Purnal and Simon Vandenhende and Lee, {Chen Yi} and Ingrid Verbauwhede and Chang, {Hsie Chia}",

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booktitle = "2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019",

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note = "2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 ; Conference date: 22-04-2019 Through 25-04-2019",

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Lu, YW, Purnal, A, Vandenhende, S, Lee, CY, Verbauwhede, I & Chang, HC 2019, A lightweight 1.16 pJ/bit processor for the authenticated encryption scheme KetjeSR. in 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019., 8741601, 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Institute of Electrical and Electronics Engineers Inc., 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Hsinchu, Taiwan, 22/04/19. https://doi.org/10.1109/VLSI-DAT.2019.8741601

A lightweight 1.16 pJ/bit processor for the authenticated encryption scheme KetjeSR. / Lu, Yun Wen; Purnal, Antoon; Vandenhende, Simon et al.
2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8741601 (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Lu YW, Purnal A, Vandenhende S, Lee CY, Verbauwhede I, Chang HC. A lightweight 1.16 pJ/bit processor for the authenticated encryption scheme KetjeSR. In 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8741601. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019). doi: 10.1109/VLSI-DAT.2019.8741601

A lightweight 1.16 pJ/bit processor for the authenticated encryption scheme KetjeSR

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