A layout-aware automatic sizing approach for retargeting analog integrated circuits

Yen Lung Chen, Yi Ching Ding, Yu Ching Liao, Hsin Ju Chang, Chien-Nan Liu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

Automatically retargeting analog designs to new technology is an efficient solution for reusing analog IPs. However, most of previous approaches focus on layout retargeting only. How to obtain the new device sizes for another technology is often not discussed. Simply scaling the device sizes may not reach the desired performance due to the non-ideal effects. Therefore, a layout-aware automatic sizing flow for retargeting analog circuits is proposed in this paper. Based on the layout template extracted from the original design, the layout-induced parasitic effects in new technology are also considered in the sizing flow. Since the possible performance degradation has been considered, no redesign cycles and reserved design margins are required in the proposed sizing flow, which significantly reduces the design overhead. As shown in the experimental results, the design retargeting can be finished in one second by using the proposed flow, which demonstrates the feasibility and efficiency of this approach.

Original languageEnglish
Title of host publication2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
DOIs
StatePublished - 15 Aug 2013
Event2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 - Hsinchu, Taiwan
Duration: 22 Apr 201324 Apr 2013

Publication series

Name2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013

Conference

Conference2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
Country/TerritoryTaiwan
CityHsinchu
Period22/04/1324/04/13

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