A Hybrid Buck Converter Stacked on Auxiliary-switched-capacitor Using Analog and Digital Dynamic Voltage Scaling Techniques

Tzu Ying Wu*, Zeng Shi-Jun, Tz Wun Wang, Sheng Cheng Lee, Ya Ting Hsu, Yu Tse Shih, Jia Rui Huang, Ke Horng Chen, Kuo Lin Zheng, Ying Hsi Lin, Shian Ru Lin, Tsung Yen Tsai

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The proposed buck stacked auxiliary-switched-capacitor architecture mainly consists of an analog and digital voltage scaling technique to achieve fast dynamic voltage scaling, and an adaptive voltage scaling technique to adapt to chip characteristics. The digital voltage scaling technique can rapidly coarse-tune the output, and the analog voltage scaling technique can fine-tune the output. The up-tracking speed can reach 0.18 μ s/ V and the down-tracking speed can reach 0.13 μ s/ V. The up and down tracking speed can be improved by 4.83X and 7.53X, (a) respectively.

Original languageEnglish
Title of host publicationESSCIRC 2023 - IEEE 49th European Solid State Circuits Conference
PublisherIEEE Computer Society
Pages429-432
Number of pages4
ISBN (Electronic)9798350304206
DOIs
StatePublished - 2023
Event49th IEEE European Solid State Circuits Conference, ESSCIRC 2023 - Lisbon, Portugal
Duration: 11 Sep 202314 Sep 2023

Publication series

NameEuropean Solid-State Circuits Conference
Volume2023-September
ISSN (Print)1930-8833

Conference

Conference49th IEEE European Solid State Circuits Conference, ESSCIRC 2023
Country/TerritoryPortugal
CityLisbon
Period11/09/2314/09/23

Keywords

  • digital voltage scaling technique
  • fast dynamic voltage scaling
  • stacked auxiliary-switched-capacitor architecture

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