A Highly Latchup-Immune 1-μm CMOS Technology Fabricated with 1-MeV Ion Implantation and Self-Aligned TiSi2

Fang Shi J. Lai, L. K. Wang, Yuan Taur, Jack Yuan Chen Sun, Karen E. Petrillo, Susan Kane Chicotka, Edward J. Petrillo, Michael R. Polcari, Thomas J. Bucelot, D. S. Zicherman

Research output: Contribution to journalArticlepeer-review

24 Scopus citations

Abstract

A 1-μm n-well CMOS technology with high latchnp immunity is designed, realized, and characterized. Important features in this technology include thin epi substrate, retrograde n-well formed by 1-MeV ion implantation, As-P graded junctions, and self-aligned ticanium disilicide. The 1-μm CMOS technology has been characterised by examining the device I-V curves, avalanche-breakdown voltages, subthreshold characteristics, short-channel effect, and sheet resistances. The devices fabricated by using the 1-MeV ion implantation and self-aligned titanium disilicide do not deviate from the conventional devices constructed with the same level of technology. With the As-P double-diffused LDD structure for the n-channel device, the avalanche-breakdown voltage is increased and hot-electron reliability is greatly improved. The titanium disilicide process effectively reduces the sheet resistances of the source-drain and the polysilicon gate to 3 Ω/□ compared with 150 Ω/□ of the unsilicided counterparts. The optimized 1-μm device channel n-well CMOS resulted in a propagation delay time of 150 ps with a power dissipation of 0.3 mW. With the thin epi wafers and the retrograde n-well structure, latchup immunity is found to be greatly improved. Moreover, with the titanium disilicide formation on the source-drain, the latchup holding voltage is found to be extremely high (13 V) with the substrate grounded from the backside of the wafer. If the backside substrate is not grounded, self-aligned disilicide over n+ and p+ regions are found necessary to ensure high latchup immunity even in the case of thin epi on heavily doped substrate. The degradation of emitter efficiency due to the TiSi2 is believed to be the dominant factor in raising the holding voltage. Detailed experimental results and discussions are presented.

Original languageEnglish
Pages (from-to)1308-1320
Number of pages13
JournalIEEE Transactions on Electron Devices
Volume33
Issue number9
DOIs
StatePublished - Sep 1986

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