A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant

Kuan Yu Lin; Ming-Dou Ker; Chun Yu Lin

doi:10.1109/ISCAS.2014.6865109

A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant

Kuan Yu Lin, Ming-Dou Ker, Chun Yu Lin

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

A biomedical stimulator with four high-voltagetolerant output channels, combined with on-chip positive high voltage generator, is proposed. For the purpose of integration with other circuit blocks into a system-on-chip (SoC) for cochlear implant biomedical applications, this design has been realized with the 1.8-V/3.3-V transistors in a 0.18-μm CMOS process. This stimulator only needs one single supply voltage of 1.8 V, but the maximum stimulation voltage can be as high as 7 V. The dynamic bias technique and stacked MOS configuration are used to implement this stimulator in the low-voltage CMOS process, without causing the issues of electrical overstress and gate-oxide reliability during circuit operation.

Original language	English
Title of host publication	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	237-240
Number of pages	4
ISBN (Print)	9781479934324
DOIs	https://doi.org/10.1109/ISCAS.2014.6865109
State	Published - 1 Jan 2014
Event	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia Duration: 1 Jun 2014 → 5 Jun 2014

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Country/Territory	Australia
City	Melbourne, VIC
Period	1/06/14 → 5/06/14

Access to Document

10.1109/ISCAS.2014.6865109

Cite this

Lin, K. Y., Ker, M-D., & Lin, C. Y. (2014). A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 (pp. 237-240). [6865109] (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2014.6865109

@inproceedings{9fad820df19d42e5b3c09d5542b795e7,

title = "A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant",

abstract = "A biomedical stimulator with four high-voltagetolerant output channels, combined with on-chip positive high voltage generator, is proposed. For the purpose of integration with other circuit blocks into a system-on-chip (SoC) for cochlear implant biomedical applications, this design has been realized with the 1.8-V/3.3-V transistors in a 0.18-μm CMOS process. This stimulator only needs one single supply voltage of 1.8 V, but the maximum stimulation voltage can be as high as 7 V. The dynamic bias technique and stacked MOS configuration are used to implement this stimulator in the low-voltage CMOS process, without causing the issues of electrical overstress and gate-oxide reliability during circuit operation.",

author = "Lin, {Kuan Yu} and Ming-Dou Ker and Lin, {Chun Yu}",

year = "2014",

month = jan,

day = "1",

doi = "10.1109/ISCAS.2014.6865109",

language = "English",

isbn = "9781479934324",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "237--240",

booktitle = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014",

address = "United States",

note = "null ; Conference date: 01-06-2014 Through 05-06-2014",

}

Lin, KY, Ker, M-D & Lin, CY 2014, A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant. in 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014., 6865109, Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., pp. 237-240, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014, Melbourne, VIC, Australia, 1/06/14. https://doi.org/10.1109/ISCAS.2014.6865109

A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant. / Lin, Kuan Yu; Ker, Ming-Dou; Lin, Chun Yu.

2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., 2014. p. 237-240 6865109 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant

AU - Lin, Kuan Yu

AU - Ker, Ming-Dou

AU - Lin, Chun Yu

PY - 2014/1/1

Y1 - 2014/1/1

N2 - A biomedical stimulator with four high-voltagetolerant output channels, combined with on-chip positive high voltage generator, is proposed. For the purpose of integration with other circuit blocks into a system-on-chip (SoC) for cochlear implant biomedical applications, this design has been realized with the 1.8-V/3.3-V transistors in a 0.18-μm CMOS process. This stimulator only needs one single supply voltage of 1.8 V, but the maximum stimulation voltage can be as high as 7 V. The dynamic bias technique and stacked MOS configuration are used to implement this stimulator in the low-voltage CMOS process, without causing the issues of electrical overstress and gate-oxide reliability during circuit operation.

AB - A biomedical stimulator with four high-voltagetolerant output channels, combined with on-chip positive high voltage generator, is proposed. For the purpose of integration with other circuit blocks into a system-on-chip (SoC) for cochlear implant biomedical applications, this design has been realized with the 1.8-V/3.3-V transistors in a 0.18-μm CMOS process. This stimulator only needs one single supply voltage of 1.8 V, but the maximum stimulation voltage can be as high as 7 V. The dynamic bias technique and stacked MOS configuration are used to implement this stimulator in the low-voltage CMOS process, without causing the issues of electrical overstress and gate-oxide reliability during circuit operation.

UR - http://www.scopus.com/inward/record.url?scp=84907398536&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2014.6865109

DO - 10.1109/ISCAS.2014.6865109

M3 - Conference contribution

AN - SCOPUS:84907398536

SN - 9781479934324

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 237

EP - 240

BT - 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 1 June 2014 through 5 June 2014

ER -

Lin KY, Ker M-D, Lin CY. A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc. 2014. p. 237-240. 6865109. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS.2014.6865109

A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant

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