A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process

Zhicong Luo; Ming-Dou Ker

doi:10.1109/TBCAS.2015.2512443

A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process

Zhicong Luo, Ming-Dou Ker

Institute of Electronics

Research output: Contribution to journal › Article › peer-review

56 Scopus citations

Abstract

This paper presents a 4 × V_DD neuro-stimulator in a 0.18-μm 1.8 V/3.3 V CMOS process. The self-adaption bias technique and stacked MOS configuration are used to prevent transistors from the electrical overstress and gate-oxide reliability issue. A high-voltage-tolerant level shifter with power-on protection is used to drive the neuro-stimulator The reliability measurement of up to 100 million periodic cycles with 3000-μA biphasic stimulations in 12-V power supply has verified that the proposed neuro-stimulator is robust. Precise charge balance is achieved by using a novel current memory cell with the dual calibration loops and leakage current compensation. The charge mismatch is down to 0.25% over all the stimulus current ranges (200-300 μA) The residual average dc current is less than 6.6 nA after shorting operation.

Original language	English
Article number	7440898
Pages (from-to)	1087-1099
Number of pages	13
Journal	IEEE Transactions on Biomedical Circuits and Systems
Volume	10
Issue number	6
DOIs	https://doi.org/10.1109/TBCAS.2015.2512443
State	Published - Dec 2016

Keywords

Charge balance
Stimulator
current memory cell
high-voltage-tolerant
leakage current compensation
level shifter

Access to Document

10.1109/TBCAS.2015.2512443

Cite this

@article{aed931be598b4d0cbd6abb2edbda9495,

title = "A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process",

abstract = "This paper presents a 4 × VDD neuro-stimulator in a 0.18-μm 1.8 V/3.3 V CMOS process. The self-adaption bias technique and stacked MOS configuration are used to prevent transistors from the electrical overstress and gate-oxide reliability issue. A high-voltage-tolerant level shifter with power-on protection is used to drive the neuro-stimulator The reliability measurement of up to 100 million periodic cycles with 3000-μA biphasic stimulations in 12-V power supply has verified that the proposed neuro-stimulator is robust. Precise charge balance is achieved by using a novel current memory cell with the dual calibration loops and leakage current compensation. The charge mismatch is down to 0.25% over all the stimulus current ranges (200-300 μA) The residual average dc current is less than 6.6 nA after shorting operation.",

keywords = "Charge balance, Stimulator, current memory cell, high-voltage-tolerant, leakage current compensation, level shifter",

author = "Zhicong Luo and Ming-Dou Ker",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.",

year = "2016",

month = dec,

doi = "10.1109/TBCAS.2015.2512443",

language = "English",

volume = "10",

pages = "1087--1099",

journal = "IEEE Transactions on Biomedical Circuits and Systems",

issn = "1932-4545",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "6",

}

TY - JOUR

T1 - A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process

AU - Luo, Zhicong

AU - Ker, Ming-Dou

PY - 2016/12

Y1 - 2016/12

N2 - This paper presents a 4 × VDD neuro-stimulator in a 0.18-μm 1.8 V/3.3 V CMOS process. The self-adaption bias technique and stacked MOS configuration are used to prevent transistors from the electrical overstress and gate-oxide reliability issue. A high-voltage-tolerant level shifter with power-on protection is used to drive the neuro-stimulator The reliability measurement of up to 100 million periodic cycles with 3000-μA biphasic stimulations in 12-V power supply has verified that the proposed neuro-stimulator is robust. Precise charge balance is achieved by using a novel current memory cell with the dual calibration loops and leakage current compensation. The charge mismatch is down to 0.25% over all the stimulus current ranges (200-300 μA) The residual average dc current is less than 6.6 nA after shorting operation.

AB - This paper presents a 4 × VDD neuro-stimulator in a 0.18-μm 1.8 V/3.3 V CMOS process. The self-adaption bias technique and stacked MOS configuration are used to prevent transistors from the electrical overstress and gate-oxide reliability issue. A high-voltage-tolerant level shifter with power-on protection is used to drive the neuro-stimulator The reliability measurement of up to 100 million periodic cycles with 3000-μA biphasic stimulations in 12-V power supply has verified that the proposed neuro-stimulator is robust. Precise charge balance is achieved by using a novel current memory cell with the dual calibration loops and leakage current compensation. The charge mismatch is down to 0.25% over all the stimulus current ranges (200-300 μA) The residual average dc current is less than 6.6 nA after shorting operation.

KW - Charge balance

KW - Stimulator

KW - current memory cell

KW - high-voltage-tolerant

KW - leakage current compensation

KW - level shifter

UR - http://www.scopus.com/inward/record.url?scp=84962617211&partnerID=8YFLogxK

U2 - 10.1109/TBCAS.2015.2512443

DO - 10.1109/TBCAS.2015.2512443

M3 - Article

C2 - 27046880

AN - SCOPUS:84962617211

SN - 1932-4545

VL - 10

SP - 1087

EP - 1099

JO - IEEE Transactions on Biomedical Circuits and Systems

JF - IEEE Transactions on Biomedical Circuits and Systems

IS - 6

M1 - 7440898

ER -

A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process

Abstract

Keywords

Access to Document

Other files and links

Fingerprint

Cite this