A high-troughput radix-4 log-MAP decoder with low complexity LLR architecture

Hsiang Tsung Chuang; Kai Hsin Tseng; Wai-Chi  Fang

doi:10.1109/VDAT.2009.5158137

A high-troughput radix-4 log-MAP decoder with low complexity LLR architecture

Hsiang Tsung Chuang^*, Kai Hsin Tseng, Wai-Chi Fang

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

The throughput of turbo decoder is limited by the recursion architecture. In this paper, an improved radix-4 recursion architecture is presented. In order to decrease the critical path delay, a hybrid 4-inputs addition/subtraction structure is employed. Moreover, we present a modified trace-back architecture to decrease the hardware complexity of the log-likelihood ratios (LLR) architecture. The area of the proposed MAP decoder is 0.58 mm² on UMC 0.13μm standard cell technology and under the worst case a maximum throughput of 600 Mbps can be achieved.

Original language	English
Title of host publication	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Pages	231-234
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2009.5158137
State	Published - 1 Dec 2009
Event	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan Duration: 28 Apr 2009 → 30 Apr 2009

Publication series

Name	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Conference

Conference	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Country/Territory	Taiwan
City	Hsinchu
Period	28/04/09 → 30/04/09

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10.1109/VDAT.2009.5158137

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@inproceedings{294b1d834cc84ee4a0f53b07035daedf,

title = "A high-troughput radix-4 log-MAP decoder with low complexity LLR architecture",

abstract = "The throughput of turbo decoder is limited by the recursion architecture. In this paper, an improved radix-4 recursion architecture is presented. In order to decrease the critical path delay, a hybrid 4-inputs addition/subtraction structure is employed. Moreover, we present a modified trace-back architecture to decrease the hardware complexity of the log-likelihood ratios (LLR) architecture. The area of the proposed MAP decoder is 0.58 mm2 on UMC 0.13μm standard cell technology and under the worst case a maximum throughput of 600 Mbps can be achieved.",

author = "Chuang, {Hsiang Tsung} and Tseng, {Kai Hsin} and Wai-Chi Fang",

year = "2009",

month = dec,

day = "1",

doi = "10.1109/VDAT.2009.5158137",

language = "English",

isbn = "9781424427826",

series = "2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09",

pages = "231--234",

booktitle = "2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09",

note = "2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 ; Conference date: 28-04-2009 Through 30-04-2009",

}

Chuang, HT, Tseng, KH & Fang, W-C 2009, A high-troughput radix-4 log-MAP decoder with low complexity LLR architecture. in 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09., 5158137, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09, pp. 231-234, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09, Hsinchu, Taiwan, 28/04/09. https://doi.org/10.1109/VDAT.2009.5158137

A high-troughput radix-4 log-MAP decoder with low complexity LLR architecture. / Chuang, Hsiang Tsung; Tseng, Kai Hsin; Fang, Wai-Chi .
2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09. 2009. p. 231-234 5158137 (2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Y1 - 2009/12/1

N2 - The throughput of turbo decoder is limited by the recursion architecture. In this paper, an improved radix-4 recursion architecture is presented. In order to decrease the critical path delay, a hybrid 4-inputs addition/subtraction structure is employed. Moreover, we present a modified trace-back architecture to decrease the hardware complexity of the log-likelihood ratios (LLR) architecture. The area of the proposed MAP decoder is 0.58 mm2 on UMC 0.13μm standard cell technology and under the worst case a maximum throughput of 600 Mbps can be achieved.

AB - The throughput of turbo decoder is limited by the recursion architecture. In this paper, an improved radix-4 recursion architecture is presented. In order to decrease the critical path delay, a hybrid 4-inputs addition/subtraction structure is employed. Moreover, we present a modified trace-back architecture to decrease the hardware complexity of the log-likelihood ratios (LLR) architecture. The area of the proposed MAP decoder is 0.58 mm2 on UMC 0.13μm standard cell technology and under the worst case a maximum throughput of 600 Mbps can be achieved.

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U2 - 10.1109/VDAT.2009.5158137

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M3 - Conference contribution

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SN - 9781424427826

T3 - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

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BT - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

T2 - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Y2 - 28 April 2009 through 30 April 2009

ER -

A high-troughput radix-4 log-MAP decoder with low complexity LLR architecture

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