A high-speed HBT prescaler based on the divideby-two topology

Hung Ju Wei*, Chin-Chun Meng, Yu Wen Chang, Yi Chen Lin, Guo Wei Huang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations


This paper demonstrates the Divide-by-4/5 prescalers with merged AND gates in 2 μm GaInP/GaAs heterojunction bipolar transistor (HBT) and 0.35 μm SiGe HBT technologies. By biasing the HBT near the peak transit-time frequency (fT), the maximum operating frequency of a D-type flip-flop (D-FF) can be promoted. At the supply voltage of 5 V, the GaInP/GaAs prescaler operates from 30 MHz to 5.2 GHz, and the SiGe prescaler has the higher-speed performance of 1 GHz ∼ 8 GHz at the cost of power consumption.

Original languageAmerican English
Title of host publication2007 Asia-Pacific Microwave Conference, APMC
ISBN (Print)1424407494, 9781424407491
StatePublished - 11 Dec 2007
EventAsia-Pacific Microwave Conference, APMC 2007 - Bangkok, Thailand
Duration: 11 Dec 200714 Dec 2007

Publication series

NameAsia-Pacific Microwave Conference Proceedings, APMC


ConferenceAsia-Pacific Microwave Conference, APMC 2007


  • Divide-by-4/5
  • Dual-modulus
  • Emitter couple logic (ECL)
  • GaInP/GaAs HBT
  • Prescaler
  • SiGe HBT


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