TY - GEN
T1 - A HIGH-RESOLUTION and LOW OFFSET DELTA-SIGMA ANALOG to DIGITAL CONVERTER for DETECTING PHOTOPLETHYSMOGRAPHY SIGNAL
AU - Pribadi, Eka Fitrah Eka Fitrah
AU - Pandey, Rajeev Kumar
AU - Chao, Paul C.P.
N1 - Publisher Copyright:
© 2021 by ASME.
PY - 2021/6/29
Y1 - 2021/6/29
N2 - A high-resolution, low offset delta-sigma analog to digital converter for detecting photoplethysmography (PPG) signal is presented in this study. The PPG signal is a bio-optical signal incorporated with heart functionality and located in the range of 0.1-10 Hz. The location to get PPG signal is on a pulsating artery. Thus the delta-sigma analog-to-digital (DS ADC) converter is designed specifically in that range. However, the DS ADC circuitry suffers from 1/f noise under 10 Hz frequency range. A chopper based operational amplifier is implemented in DS ADC to push the 1/f noise into high-frequency noise. The dc offset of the operational amplifier is also pushed to the highfrequency region. The DS ADC circuitry consists of a secondorder continuous-time delta-sigma modulator. The delta-sigma modulator circuitry is designed and simulated using TSMC 180 nm technology. The continuous-time delta-sigma modulator active area layout is 746m × 399 m and fabricated using TSMC 180 nm technology. It operates in 100 Hz bandwidth and 4096 over-sampling ratios. The SFDR of the circuit is above 70 dB. The power consumption of the delta-sigma modulator is 35.61W. The simulation is performed in three different kinds of corner, SS, TT, and FF corner, to guarantee the circuitry works in different conditions.
AB - A high-resolution, low offset delta-sigma analog to digital converter for detecting photoplethysmography (PPG) signal is presented in this study. The PPG signal is a bio-optical signal incorporated with heart functionality and located in the range of 0.1-10 Hz. The location to get PPG signal is on a pulsating artery. Thus the delta-sigma analog-to-digital (DS ADC) converter is designed specifically in that range. However, the DS ADC circuitry suffers from 1/f noise under 10 Hz frequency range. A chopper based operational amplifier is implemented in DS ADC to push the 1/f noise into high-frequency noise. The dc offset of the operational amplifier is also pushed to the highfrequency region. The DS ADC circuitry consists of a secondorder continuous-time delta-sigma modulator. The delta-sigma modulator circuitry is designed and simulated using TSMC 180 nm technology. The continuous-time delta-sigma modulator active area layout is 746m × 399 m and fabricated using TSMC 180 nm technology. It operates in 100 Hz bandwidth and 4096 over-sampling ratios. The SFDR of the circuit is above 70 dB. The power consumption of the delta-sigma modulator is 35.61W. The simulation is performed in three different kinds of corner, SS, TT, and FF corner, to guarantee the circuitry works in different conditions.
KW - CT-DSM
KW - PPG Signal
KW - chopper stabilization
UR - http://www.scopus.com/inward/record.url?scp=85109404060&partnerID=8YFLogxK
U2 - 10.1115/ISPS2021-65248
DO - 10.1115/ISPS2021-65248
M3 - Conference contribution
AN - SCOPUS:85109404060
T3 - Proceedings of the ASME 2021 30th Conference on Information Storage and Processing Systems, ISPS 2021
BT - Proceedings of the ASME 2021 30th Conference on Information Storage and Processing Systems, ISPS 2021
PB - American Society of Mechanical Engineers (ASME)
T2 - ASME 2021 30th Conference on Information Storage and Processing Systems, ISPS 2021
Y2 - 2 June 2021 through 3 June 2021
ER -