A high-performance low V MIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control

Hao I. Yang; Shih Chi Yang; Mao Chih Hsia; Yung Wei Lin; Yi Wei Lin; Chien Hen Chen; Chi Shin Chang; Geng Cing Lin; Yin Nien Chen; Ching Te Chuang; Wei Hwang; Shyh-Jye Jou; Nan Chun Lien; Hung Yu Li; Kuen Di Lee; Wei Chiang Shih; Ya Ping Wu; Wen Ta Lee; Chih Chiang Hsu

doi:10.1109/SOCC.2011.6085080

A high-performance low V _MIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control

Hao I. Yang^*, Shih Chi Yang, Mao Chih Hsia, Yung Wei Lin, Yi Wei Lin, Chien Hen Chen, Chi Shin Chang, Geng Cing Lin, Yin Nien Chen, Ching Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan Chun Lien, Hung Yu Li, Kuen Di Lee, Wei Chiang Shih, Ya Ping Wu, Wen Ta Lee, Chih Chiang Hsu

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Scopus citations

Abstract

This paper describes a high-performance low V _MIN SRAM with a disturb-free 8T cell. The SRAM utilizes single-ended buffer Read, and cross-point data-aware Write Word-Line structure with adaptive VVSS control to eliminate Read disturb and Half-Select disturb, thus facilitating bit-interleaving architecture and achieving low V _MIN. A 512Kb test chip is implemented in UMC 55nm Standard Performance (SP) CMOS technology. The measurement results demonstrate operating frequency of 943MHz at 1.2V VDD and 209MHz at 0.6V VDD.

Original language	English
Title of host publication	Proceedings - IEEE International SOC Conference, SOCC 2011
Pages	197-200
Number of pages	4
DOIs	https://doi.org/10.1109/SOCC.2011.6085080
State	Published - 28 Dec 2011
Event	24th IEEE International System on Chip Conference, SOCC 2011 - Taipei, Taiwan Duration: 26 Sep 2011 → 28 Sep 2011

Publication series

Name	International System on Chip Conference
ISSN (Print)	2164-1676
ISSN (Electronic)	2164-1706

Conference

Conference	24th IEEE International System on Chip Conference, SOCC 2011
Country/Territory	Taiwan
City	Taipei
Period	26/09/11 → 28/09/11

Access to Document

10.1109/SOCC.2011.6085080

Cite this

Yang, H. I., Yang, S. C., Hsia, M. C., Lin, Y. W., Lin, Y. W., Chen, C. H., Chang, C. S., Lin, G. C., Chen, Y. N., Chuang, C. T., Hwang, W., Jou, S.-J., Lien, N. C., Li, H. Y., Lee, K. D., Shih, W. C., Wu, Y. P., Lee, W. T., & Hsu, C. C. (2011). A high-performance low V _MIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. In Proceedings - IEEE International SOC Conference, SOCC 2011 (pp. 197-200). Article 6085080 (International System on Chip Conference). https://doi.org/10.1109/SOCC.2011.6085080

@inproceedings{692bb75e6393464cbbffa63bdcc10282,

title = "A high-performance low V MIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control",

abstract = "This paper describes a high-performance low V MIN SRAM with a disturb-free 8T cell. The SRAM utilizes single-ended buffer Read, and cross-point data-aware Write Word-Line structure with adaptive VVSS control to eliminate Read disturb and Half-Select disturb, thus facilitating bit-interleaving architecture and achieving low V MIN. A 512Kb test chip is implemented in UMC 55nm Standard Performance (SP) CMOS technology. The measurement results demonstrate operating frequency of 943MHz at 1.2V VDD and 209MHz at 0.6V VDD.",

author = "Yang, {Hao I.} and Yang, {Shih Chi} and Hsia, {Mao Chih} and Lin, {Yung Wei} and Lin, {Yi Wei} and Chen, {Chien Hen} and Chang, {Chi Shin} and Lin, {Geng Cing} and Chen, {Yin Nien} and Chuang, {Ching Te} and Wei Hwang and Shyh-Jye Jou and Lien, {Nan Chun} and Li, {Hung Yu} and Lee, {Kuen Di} and Shih, {Wei Chiang} and Wu, {Ya Ping} and Lee, {Wen Ta} and Hsu, {Chih Chiang}",

year = "2011",

month = dec,

day = "28",

doi = "10.1109/SOCC.2011.6085080",

language = "English",

isbn = "9781457716164",

series = "International System on Chip Conference",

pages = "197--200",

booktitle = "Proceedings - IEEE International SOC Conference, SOCC 2011",

note = "24th IEEE International System on Chip Conference, SOCC 2011 ; Conference date: 26-09-2011 Through 28-09-2011",

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Yang, HI, Yang, SC, Hsia, MC, Lin, YW, Lin, YW, Chen, CH, Chang, CS, Lin, GC, Chen, YN, Chuang, CT, Hwang, W, Jou, S-J, Lien, NC, Li, HY, Lee, KD, Shih, WC, Wu, YP, Lee, WT & Hsu, CC 2011, A high-performance low V _MIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. in Proceedings - IEEE International SOC Conference, SOCC 2011., 6085080, International System on Chip Conference, pp. 197-200, 24th IEEE International System on Chip Conference, SOCC 2011, Taipei, Taiwan, 26/09/11. https://doi.org/10.1109/SOCC.2011.6085080

A high-performance low V _MIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. / Yang, Hao I.; Yang, Shih Chi; Hsia, Mao Chih et al.
Proceedings - IEEE International SOC Conference, SOCC 2011. 2011. p. 197-200 6085080 (International System on Chip Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Lin, Yi Wei

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AU - Chang, Chi Shin

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AU - Chen, Yin Nien

AU - Chuang, Ching Te

AU - Hwang, Wei

AU - Jou, Shyh-Jye

AU - Lien, Nan Chun

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AB - This paper describes a high-performance low V MIN SRAM with a disturb-free 8T cell. The SRAM utilizes single-ended buffer Read, and cross-point data-aware Write Word-Line structure with adaptive VVSS control to eliminate Read disturb and Half-Select disturb, thus facilitating bit-interleaving architecture and achieving low V MIN. A 512Kb test chip is implemented in UMC 55nm Standard Performance (SP) CMOS technology. The measurement results demonstrate operating frequency of 943MHz at 1.2V VDD and 209MHz at 0.6V VDD.

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