A high-performance area-aware DSP processor architecture for video codecs

Lan-Da Van*, Hsin Fu Luo, Chien Ming Wu, Wen Hsiang Hu, Chun Ming Huang, Wei Chang Tsai

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In this paper, we propose a high-performance and area-aware very long instruction word (VLIW) DSP architecture using a flexible single instruction multiple data (SIMD) approach and a grouped permutation (GP) structure register file, respectively. Via the proposed data path architecture, the reduction of the execution cycles for digital filter and RGB2YUV benchmarks can be improved up to 50% compared with that of [8, 11]. For motion estimation, the number of pixels per cycle applying the proposed architecture can be four times than that of [8, 11]. For the register file, using proposed GP structure, the saving of switching network overhead could be anticipated compared with the work in [11].

Original languageEnglish
Title of host publication2004 IEEE International Conference on Multimedia and Expo (ICME)
Pages1499-1502
Number of pages4
DOIs
StatePublished - 1 Dec 2004
Event2004 IEEE International Conference on Multimedia and Expo (ICME) - Taipei, Taiwan
Duration: 27 Jun 200430 Jun 2004

Publication series

Name2004 IEEE International Conference on Multimedia and Expo (ICME)
Volume3

Conference

Conference2004 IEEE International Conference on Multimedia and Expo (ICME)
Country/TerritoryTaiwan
CityTaipei
Period27/06/0430/06/04

Fingerprint

Dive into the research topics of 'A high-performance area-aware DSP processor architecture for video codecs'. Together they form a unique fingerprint.

Cite this