A high performance 0.15 μm CMOS

G. G. Shahidi, J. Warnock, A. Acovic, P. Agnello, C. Blair, T. Bucelot, A. Burghartz, E. Crabbe, J. Cressler, P. Coane, J. Comfort, B. Davari, S. Fischer, E. Ganin, S. Gittleman, J. Keller, K. Jenkins, D. Klaus, K. Kiewtniak, T. LiiP. A. McFarland, T. Ning, M. Polcari, S. Subbana, J. Y. Sun, D. Sunderland, A. C. Warren, C. Wong

Research output: Contribution to journalConference articlepeer-review

28 Scopus citations


In this paper a CMOS technology with the nominal channel length of 0.15 fim and minimum channel length below 0.1 μm is presented. Loaded NAND (FI=FO=3, CL,=240 fF) delay of 200 psec and unloaded delay of 33 psec at supply voltage of 1.8 V is demonstrated. In order to minimize short channel effects down to channel length below 0.1 μm, highly non-uniform channel doping obtained by indium and antimony, and source-drain extensions were utilized. To minimze the gate RC, a polycide stack gate structure was used.

Original languageEnglish
Article number760261
Pages (from-to)93-94
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
StatePublished - 1993
Event1993 13th Symposium on VLSI Technology, VLSIT 1993 - Kyoto, Japan
Duration: 17 May 199319 May 1993


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