A hardware-efficient VLSI implementation of a 4-channel ICA processor for biomedical signal measurement

Chiu Kuo Chen; Ericson Chua; Chih Chung Fu; Shao Yen Tseng; Wai-Chi  Fang

doi:10.1109/ICCE.2011.5722766

A hardware-efficient VLSI implementation of a 4-channel ICA processor for biomedical signal measurement

Chiu Kuo Chen^*, Ericson Chua, Chih Chung Fu, Shao Yen Tseng, Wai-Chi Fang

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Scopus citations

Abstract

This paper presents a 4-channel ICA implementation in the separation of EEG signals for on-line monitoring and analysis of brain functionalities. A novel ICA architecture utilizing mixed sequential, pipelined, and parallel processing units and employing interleaved and circular-based RAM modules to achieve hardware-efficient design is presented. The ICA processor is fabricated using UMC 90nm High-Vt CMOS technology.

Original language	English
Title of host publication	2011 IEEE International Conference on Consumer Electronics, ICCE 2011
Pages	607-608
Number of pages	2
DOIs	https://doi.org/10.1109/ICCE.2011.5722766
State	Published - 28 Mar 2011
Event	2011 IEEE International Conference on Consumer Electronics, ICCE 2011 - Las Vegas, NV, United States Duration: 9 Jan 2011 → 12 Jan 2011

Publication series

Name	Digest of Technical Papers - IEEE International Conference on Consumer Electronics
ISSN (Print)	0747-668X

Conference

Conference	2011 IEEE International Conference on Consumer Electronics, ICCE 2011
Country/Territory	United States
City	Las Vegas, NV
Period	9/01/11 → 12/01/11

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10.1109/ICCE.2011.5722766

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Chen, C. K., Chua, E., Fu, C. C., Tseng, S. Y., & Fang, W-C. (2011). A hardware-efficient VLSI implementation of a 4-channel ICA processor for biomedical signal measurement. In 2011 IEEE International Conference on Consumer Electronics, ICCE 2011 (pp. 607-608). Article 5722766 (Digest of Technical Papers - IEEE International Conference on Consumer Electronics). https://doi.org/10.1109/ICCE.2011.5722766

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title = "A hardware-efficient VLSI implementation of a 4-channel ICA processor for biomedical signal measurement",

abstract = "This paper presents a 4-channel ICA implementation in the separation of EEG signals for on-line monitoring and analysis of brain functionalities. A novel ICA architecture utilizing mixed sequential, pipelined, and parallel processing units and employing interleaved and circular-based RAM modules to achieve hardware-efficient design is presented. The ICA processor is fabricated using UMC 90nm High-Vt CMOS technology.",

author = "Chen, {Chiu Kuo} and Ericson Chua and Fu, {Chih Chung} and Tseng, {Shao Yen} and Wai-Chi Fang",

year = "2011",

month = mar,

day = "28",

doi = "10.1109/ICCE.2011.5722766",

language = "English",

isbn = "9781424487127",

series = "Digest of Technical Papers - IEEE International Conference on Consumer Electronics",

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booktitle = "2011 IEEE International Conference on Consumer Electronics, ICCE 2011",

note = "2011 IEEE International Conference on Consumer Electronics, ICCE 2011 ; Conference date: 09-01-2011 Through 12-01-2011",

}

Chen, CK, Chua, E, Fu, CC, Tseng, SY & Fang, W-C 2011, A hardware-efficient VLSI implementation of a 4-channel ICA processor for biomedical signal measurement. in 2011 IEEE International Conference on Consumer Electronics, ICCE 2011., 5722766, Digest of Technical Papers - IEEE International Conference on Consumer Electronics, pp. 607-608, 2011 IEEE International Conference on Consumer Electronics, ICCE 2011, Las Vegas, NV, United States, 9/01/11. https://doi.org/10.1109/ICCE.2011.5722766

A hardware-efficient VLSI implementation of a 4-channel ICA processor for biomedical signal measurement. / Chen, Chiu Kuo; Chua, Ericson; Fu, Chih Chung et al.
2011 IEEE International Conference on Consumer Electronics, ICCE 2011. 2011. p. 607-608 5722766 (Digest of Technical Papers - IEEE International Conference on Consumer Electronics).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This paper presents a 4-channel ICA implementation in the separation of EEG signals for on-line monitoring and analysis of brain functionalities. A novel ICA architecture utilizing mixed sequential, pipelined, and parallel processing units and employing interleaved and circular-based RAM modules to achieve hardware-efficient design is presented. The ICA processor is fabricated using UMC 90nm High-Vt CMOS technology.

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A hardware-efficient VLSI implementation of a 4-channel ICA processor for biomedical signal measurement

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