In this paper, we extend our generalized methodology for designing lower-error area-efficient fixed-width two's-complement multipliers that receive two s-bit numbers and produce an s-bit product. The generalized methodology involving four steps results in several better error-compensation biases. These better error-compensation biases can be easily mapped to lower-error fixed-width multipliers suitable for VLSI realization.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 1 Jan 2002|