A General and Automatic Cell Layout Generation Framework With Implicit Learning on Design Rules

Aaron C.W. Liang, Charles H.P. Wen, Hsuan Ming Huang

Research output: Contribution to journalArticlepeer-review


Design rule (DR) is the most critical challenge for generating a cell layout automatically in the advanced process technologies (e.g., finFET-EUV). Previous works explicitly encode the complicated DRs into routing constraints and automation scripts, which may not be general and efficient for addressing the DR problem. Therefore, an automatic cell layout generation (ACLG) framework is proposed and adopts three implicit-learning techniques i.e., guidance learning (EGL), DR learning (DRL), and mistake-driven learning (MDL), which jointly discover the knowledge of complex DRs from the existing layouts in the cell library. EGL learns the geometry behavior of the target metals from the legal cell layouts. DRL learns the DRs from layout patterns. MDL learns the routing constraints iteratively from the encountered mistakes during the layout generation (LG). These three implicit-learning techniques are combined into ACLG and developed into four core stages to cope with the DR challenge in a more general and efficient way. The experimental results demonstrate that ACLG effectively solves all the DR violations (DRVs) in an advanced finFET-EUV process (100% success rate on fixing DRVs) and successfully yields DRC-clean cell layouts for 13 benchmark cells. In addition, the proposed DRL technique is more efficient than the commercial DRC tool in excluding the illegal layout solution space. The number of iterations for a generated legal cell layout is reduced by 30% on average with DRL (3.31) compared to the commercial DRC tool (4.69). Moreover, the total runtime of generating legal layouts for 13 benchmark cells is further improved by 2.57<inline-formula> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> on average. Since DRL not only reduces the iterations of refining the DRVs in the generated cells but also speedups the process of DR checking (DRC) efficiently.

Original languageEnglish
Pages (from-to)1-14
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
StateAccepted/In press - 2022


  • Design rule (DR)
  • finFET-EUV
  • Integrated circuits
  • Law
  • Layout
  • layout generation (LG)
  • machine learning
  • Manuals
  • Metals
  • neural network (NN)
  • Routing
  • standard cell
  • Standards


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