A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC's

Ming-Dou Ker*, Hun Hsien Chang, Chung-Yu Wu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

71 Scopus citations


A novel electrostatic discharge (ESD) protection circuit, which combines complementary low-voltage-triggered lateral SCR (LVTSCR) devices and the gate-coupling technique, is proposed to effectively protect the thinner gate oxide of deep submicron CMOS IC's without adding an extra ESD-implant mask. Gate-coupling technique is used to couple the ESD-transient voltage to the gates of the PMOS-triggered/NMOS-triggered lateral silicon controlled rectifier (SCR) (PTLSCR/NTLSCR) devices to turn on the lateral SCR devices during an ESD stress. The trigger voltage of gate-coupled lateral SCR devices can be significantly reduced by the coupling capacitor. Thus, the thinner gate oxide of the input buffers in deep-submicron low-voltage CMOS IC's can be fully protected against ESD damage. Experimental results have verified that this proposed ESD protection circuit with a trigger voltage about 7 V can provide 4.8 (3.3) times human-body-model (HBM) [machine-model (MM)] ESD failure levels while occupying 47% of layout area, as compared with a conventional CMOS ESD protection circuit.

Original languageEnglish
Pages (from-to)38-50
Number of pages13
JournalIEEE Journal of Solid-State Circuits
Issue number1
StatePublished - Jan 1997


  • Charged-device model
  • ESD protection circuit
  • ESD-implant process
  • Electrostatic discharge
  • Gate-couple technique
  • Human-body model
  • Low-voltage-triggered lateral SCR
  • Machine model
  • NMOS-triggered lateral SCR
  • PMOS-triggered lateral SCR


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