TY - JOUR
T1 - A GaN-on-Si Gate Driver With Self-Pumped Drive Enhance and Short-Period Negative Voltage Techniques for Reduction of 14.7× Tailing Power Loss and 37% Reverse Conduction Loss
AU - Tsai, Hsing Yen
AU - Chen, Ke Horng
AU - Zheng, Kuo Lin
AU - Lin, Ying Hsi
AU - Lin, Shian Ru
AU - Tsai, Tsung Yen
N1 - Publisher Copyright:
© 1966-2012 IEEE.
PY - 2024/3/1
Y1 - 2024/3/1
N2 - The gallium nitride (GaN)-on-Si low-side gate driver proposed in this article has four main features: First, the self-pumped drive enhance (SPDE) technique achieves fast transients. Second, short-period negative voltage (SPNV) technique avoids the Miller coupling effect and improves efficiency. Third, a dual-mode Voltage regulator ensures sufficient current and minimizes power dissipation. Finally, monolithic low-side gate drivers provide robust drive capability. This work can suppress the ringing caused by high dV/dt of VDS, thereby minimizing the tail time Ttail, achieving a 14.7× reduction in tailing current loss, suppressing abnormal conduction, and reducing reverse conduction loss by 37.0%.
AB - The gallium nitride (GaN)-on-Si low-side gate driver proposed in this article has four main features: First, the self-pumped drive enhance (SPDE) technique achieves fast transients. Second, short-period negative voltage (SPNV) technique avoids the Miller coupling effect and improves efficiency. Third, a dual-mode Voltage regulator ensures sufficient current and minimizes power dissipation. Finally, monolithic low-side gate drivers provide robust drive capability. This work can suppress the ringing caused by high dV/dt of VDS, thereby minimizing the tail time Ttail, achieving a 14.7× reduction in tailing current loss, suppressing abnormal conduction, and reducing reverse conduction loss by 37.0%.
KW - Dual-mode voltage regulator
KW - gallium nitride (GaN)-on-Si
KW - monolithic low-side gate driver
KW - self-pumped drive enhance (SPDE) technique
KW - short-period negative voltage (SPNV) technique
UR - http://www.scopus.com/inward/record.url?scp=85179054765&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2023.3331153
DO - 10.1109/JSSC.2023.3331153
M3 - Article
AN - SCOPUS:85179054765
SN - 0018-9200
VL - 59
SP - 784
EP - 793
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 3
ER -