A GaN-on-Si Gate Driver with 14.7X Reduction in Tailing Current Loss and 37.0% Reduction of Reverse Conduction Loss

Hsing Yen Tsai*, Kuo Lin Zheng, Ke Horng Chen, Ying Hsi Lin, Shian Ru Lin, Tsung Yen Tsai

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

GaN switches are widely used in high switching and high power density power converter designs due to their low on-resistance and low input capacitance. Monolithic GaN solutions can provide high drive capability and high switching frequency due to low parasitic effects [1-3]. However, due to the highly integrated solution, some abnormal operations may affect the overall performance. High dV/dt caused by high input voltage (100 to 650V) will induce abnormal operation when the GaN turns on and off. Especially, the gate control voltage of the low-side GaN switch in the half-bridge structure will have the ringing problem, which is caused by the coupling effects from the drain-to-gate capacitance (CDG) in case of large dV/dt. State-of-the-art gate driver uses segment drive currents to speed up and stabilize the gate drive voltage. Although, the gate drive current 1_G in Fig. 1 is reduced to 1_G(\min) to suppress the inrush current during the Miller Plateau period, the low drive capability will suffer from a large ringing problem [1], [4-6]. When VD is lower than VG, 1_G needs to provide 1_GD and 1_GS. The VG will experience a voltage dip. More drive current is needed from the internal voltage regulator. Owing to the sudden demand for drive current, the voltage regulator may suffer from another voltage dip and deteriorate the ringing effect at VG. More seriously, the VG may drop below the VTH to cause the abnormal turn-off effect of the low side GaN switch. The drian-tosource voltage VDS will suffer from a large tailing time T_tai12 which is larger than T_tai11 in the case with only the coupling effect. The tailing time is defined as the time that the no tailing point to the time that VDS falls to zero. Furthermore, the power loss of the tailing current can be expressed as T_tai1V_PL/(T_fai1V_DS+T_tai1V_PL) where VPL is the Miller Plateau voltage. Minimizing T_tai1 can improve efficiency. In [7], an additional pull-up current can be provided by O_E5 if the VG drops below 2V_DDR-2V_TH. Unfortunately, the 1R drop effect at the supply voltage VDD will cause a large voltage dip at VDDR. The main drive GaNO_E7 and additional drive GaNO_E5 will lose their drive capability at the same time. Therefore, in this paper, the proposed SelfPumped Drive Enhance (SPDE) technique can suppress the ringing to minimize the tailing time T_tai1 to its ideal value.

Original languageEnglish
Title of host publication2023 IEEE Custom Integrated Circuits Conference, CICC 2023 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350399486
DOIs
StatePublished - 2023
Event44th Annual IEEE Custom Integrated Circuits Conference, CICC 2023 - San Antonio, United States
Duration: 23 Apr 202326 Apr 2023

Publication series

NameProceedings of the Custom Integrated Circuits Conference
Volume2023-April
ISSN (Print)0886-5930

Conference

Conference44th Annual IEEE Custom Integrated Circuits Conference, CICC 2023
Country/TerritoryUnited States
CitySan Antonio
Period23/04/2326/04/23

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