A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories

Yi Hsun Chen; Chi Heng Yang; Hsie-Chia Chang

doi:10.1109/VLSI-DAT.2012.6212602

A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories

Yi Hsun Chen^*, Chi Heng Yang, Hsie-Chia Chang

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Scopus citations

Abstract

This paper presents a (274,256,2) DEC BCH decoder for NOR flash memories to improve the reliability. From the step-by-step algorithm, the decoding mechanism can be derived from a simple checking equation and its fully-parallel architecture is implemented to meet the low latency requirement. Moreover, the composite field arithmetic without extra field conversion hardware is applied to the whole decoder for further reducing complexity. By using UMC 90 nm CMOS technology, the synthesis results show that the latency is 2.5 ns with 23.2K logic gates.

Original language	English
Title of host publication	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
DOIs	https://doi.org/10.1109/VLSI-DAT.2012.6212602
State	Published - 2012
Event	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Hsinchu, Taiwan Duration: 23 Apr 2012 → 25 Apr 2012

Publication series

Name	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

Conference

Conference	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
Country/Territory	Taiwan
City	Hsinchu
Period	23/04/12 → 25/04/12

Keywords

BCH codes
Composite field
Double-Error-Correcting
NOR flash memories
Step-by-step decoding algorithm

Access to Document

10.1109/VLSI-DAT.2012.6212602

Cite this

Chen, Y. H., Yang, C. H., & Chang, H.-C. (2012). A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories. In 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers Article 6212602 (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers). https://doi.org/10.1109/VLSI-DAT.2012.6212602

Chen, Yi Hsun ; Yang, Chi Heng ; Chang, Hsie-Chia. / A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories. 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers).

@inproceedings{9c11508dffde4428ba0cb7100ae4dd1e,

title = "A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories",

abstract = "This paper presents a (274,256,2) DEC BCH decoder for NOR flash memories to improve the reliability. From the step-by-step algorithm, the decoding mechanism can be derived from a simple checking equation and its fully-parallel architecture is implemented to meet the low latency requirement. Moreover, the composite field arithmetic without extra field conversion hardware is applied to the whole decoder for further reducing complexity. By using UMC 90 nm CMOS technology, the synthesis results show that the latency is 2.5 ns with 23.2K logic gates.",

keywords = "BCH codes, Composite field, Double-Error-Correcting, NOR flash memories, Step-by-step decoding algorithm",

author = "Chen, {Yi Hsun} and Yang, {Chi Heng} and Hsie-Chia Chang",

year = "2012",

doi = "10.1109/VLSI-DAT.2012.6212602",

language = "English",

isbn = "9781457720819",

series = "2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers",

booktitle = "2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers",

note = "2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 ; Conference date: 23-04-2012 Through 25-04-2012",

}

Chen, YH, Yang, CH & Chang, H-C 2012, A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories. in 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers., 6212602, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012, Hsinchu, Taiwan, 23/04/12. https://doi.org/10.1109/VLSI-DAT.2012.6212602

A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories. / Chen, Yi Hsun; Yang, Chi Heng; Chang, Hsie-Chia.
2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. 6212602 (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Yang, Chi Heng

AU - Chang, Hsie-Chia

PY - 2012

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N2 - This paper presents a (274,256,2) DEC BCH decoder for NOR flash memories to improve the reliability. From the step-by-step algorithm, the decoding mechanism can be derived from a simple checking equation and its fully-parallel architecture is implemented to meet the low latency requirement. Moreover, the composite field arithmetic without extra field conversion hardware is applied to the whole decoder for further reducing complexity. By using UMC 90 nm CMOS technology, the synthesis results show that the latency is 2.5 ns with 23.2K logic gates.

AB - This paper presents a (274,256,2) DEC BCH decoder for NOR flash memories to improve the reliability. From the step-by-step algorithm, the decoding mechanism can be derived from a simple checking equation and its fully-parallel architecture is implemented to meet the low latency requirement. Moreover, the composite field arithmetic without extra field conversion hardware is applied to the whole decoder for further reducing complexity. By using UMC 90 nm CMOS technology, the synthesis results show that the latency is 2.5 ns with 23.2K logic gates.

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KW - Composite field

KW - Double-Error-Correcting

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KW - Step-by-step decoding algorithm

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M3 - Conference contribution

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SN - 9781457720819

T3 - 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

BT - 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

T2 - 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012

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Chen YH, Yang CH, Chang HC. A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories. In 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. 6212602. (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers). doi: 10.1109/VLSI-DAT.2012.6212602

A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories

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