A fully parallel BCH codec with double error correcting capability for NOR flash applications

Chia Ching Chu*, Yi Min Lin, Chi Heng Yang, Hsie-Chia Chang

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    12 Scopus citations

    Abstract

    A double error correcting (DEC) BCH codec is designed for NOR flash memory systems to improve reliability. Due to the latency constraint less than 10 ns, the fully parallel architecture with huge hardware cost is utilized to process both the encoding and decoding scheme within one clock cycle. Notice that encoder and decoder will not be activated simultaneously in NOR flash applications, so we combine the encoder and syndrome calculator based on the property of minimal polynomials in order to efficiently arrange silicon area. Furthermore, a new error location polynomial is developed to reduce the number of constant finite filed multipliers (CFFMs) in Chien search. According to 90 nm CMOS technology, our propose DEC BCH codec can achieve 2.5 ns latency with 41,705 μm 2 area.

    Original languageEnglish
    Title of host publication2012 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2012 - Proceedings
    Pages1605-1608
    Number of pages4
    DOIs
    StatePublished - 23 Oct 2012
    Event2012 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2012 - Kyoto, Japan
    Duration: 25 Mar 201230 Mar 2012

    Publication series

    NameICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
    ISSN (Print)1520-6149

    Conference

    Conference2012 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2012
    Country/TerritoryJapan
    CityKyoto
    Period25/03/1230/03/12

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