A Fully Integrated GaN-on-Silicon Gate Driver and GaN Switch with Temperature-compensated Fast Turn-on Technique for Improving Reliability

Hsuan Yu Chen, Yu Yung Kao, Zhi Qiang Zhang, Cheng Hsiang Liao, Hong Yuan Yang, Ming Sheng Hsu, Ke-Horng Chen, Ying Hsi Lin, Shian Ru Lin, Tsung Yen Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

33 Scopus citations

Abstract

Gallium-Nitride (GaN) high-electron-mobility transistors (HEMTs) have the advantages of low parasitic capacitance, low on-resistance (R_{ON}), and no reverse recovery charge loss [1-5]. Thus, using GaN HEMTs one can optimize the performance of power integrated circuits. However, today's GaN HEMTs have serious process defects, especially depending on the selected substrate. A 650V GaN-on-Si structure is shown in Fig. 33.1.1, and there are severe heterogeneous defects between the GaN buffer layer and the Si substrate. Thus, temperature changes will seriously aggravate the hot carrier injection, and the two-dimensional electron gas (2DEG) layer in the GaN HEMT will weaken over time. The on-resistance (R_{ON}) and threshold voltage (V_{TH,E}) of 650 GaN HEMT gradually increase, and in turn, rapidly decline the reliability. Although state-of the-art gate drivers can effectively reduce the ringing at the VGS of the GaN switch [4-6], the temperature reliability problem still exists. The tri-slope gate control in [4] adjusts the sourcing current IControl to drive the gate voltage VG. The active slew-rate control method in [6] uses different gate resistors RG1 and RG2 to control the driving current IG. Both control techniques did not consider temperature-dependent threshold voltage. To completely reduce parasitic effects, monolithic integration of gate driver and GaN HEMT in GaN-on-Si process has been shown in [3, 7]. However, they did not carefully consider the reliability degradation caused by the variations of V_{TH,E} and Miller plateau voltage due to temperature effects. High switching operations enlarge the temperature effect on monolithic integration.

Original languageEnglish
Title of host publication2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages460-462
Number of pages3
ISBN (Electronic)9781728195490
DOIs
StatePublished - 13 Feb 2021
Event2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 - San Francisco, United States
Duration: 13 Feb 202122 Feb 2021

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume64
ISSN (Print)0193-6530

Conference

Conference2021 IEEE International Solid-State Circuits Conference, ISSCC 2021
Country/TerritoryUnited States
CitySan Francisco
Period13/02/2122/02/21

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