A full E-beam 0.25 mu m bipolar technology with sub-25 ps ECL gate delay

J. Warnock, J. D. Cressler, P. J. Coane, K. N. Chiong, M. E. Rothwell, K. Jenkins, J. N. Burghartz, E. Petrillo, N. Mazzeo, A. Megdanis, F. J. Hohn, M. G.R. Thomson, J. Y.C. Sun, D. D. Tang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

Summary form only given. The full leverage offered by E-beam lithography has been exploited in a 0.25- mu m bipolar process. The tight overlay capability was shown to provide a significant advantage in shrinking the overall transistor size. In conjunction with a device technology optimized to provide a 33-GHz 0.25- mu m-emitter device, this culminated in the achievement of an ECL (emitter coupled logic) delay of 24 ps at a switching current of only 1.1 mA.

Original languageEnglish
Title of host publicationInternational Electron Devices Meeting 1991, IEDM 1991
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages956-958
Number of pages3
ISBN (Electronic)0780302435
DOIs
StatePublished - 1991
EventInternational Electron Devices Meeting, IEDM 1991 - Washington, United States
Duration: 8 Dec 199111 Dec 1991

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
Volume1991-January
ISSN (Print)0163-1918

Conference

ConferenceInternational Electron Devices Meeting, IEDM 1991
Country/TerritoryUnited States
CityWashington
Period8/12/9111/12/91

Keywords

  • Capacitors
  • Circuit simulation
  • Cutoff frequency
  • Delay
  • Electrons
  • Lithography
  • Personnel
  • Predictive models
  • Switches
  • Transistors

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