A fourth-order incremental ADC in three-step

Jia Sheng Huang; Shih Che Kuo; Chia Wei Kao; Yu Cheng Huang; Che Wei Hsu; Chia Hung Chen

doi:10.1049/tje2.12044

A fourth-order incremental ADC in three-step

Jia Sheng Huang, Shih Che Kuo, Chia Wei Kao, Yu Cheng Huang, Che Wei Hsu, Chia Hung Chen^*

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

Abstract

This letter presents a second-order incremental ADC (IADC) operated in three steps, which extends the performance of a second-order IADC close to that of a fourth-order IADC with only two amplifiers. It performs a second-order noise-shaping quantization in the first step operation. Reusing the same hardware, the circuit is reconfigured to perform fine quantization as a first-order IADC in the second and third step. Within a conversion time of 60 clock periods (oversampling ratio OSR = 60), 35 dB signal-to-quantization-noise ratio is boosted. The proposed topology is very suitable for low-bandwidth high-resolution data conversion.

Original language	English
Pages (from-to)	394-398
Number of pages	5
Journal	Journal of Engineering
Volume	2021
Issue number	7
DOIs	https://doi.org/10.1049/tje2.12044
State	Published - Jul 2021

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title = "A fourth-order incremental ADC in three-step",

abstract = "This letter presents a second-order incremental ADC (IADC) operated in three steps, which extends the performance of a second-order IADC close to that of a fourth-order IADC with only two amplifiers. It performs a second-order noise-shaping quantization in the first step operation. Reusing the same hardware, the circuit is reconfigured to perform fine quantization as a first-order IADC in the second and third step. Within a conversion time of 60 clock periods (oversampling ratio OSR = 60), 35 dB signal-to-quantization-noise ratio is boosted. The proposed topology is very suitable for low-bandwidth high-resolution data conversion.",

author = "Huang, {Jia Sheng} and Kuo, {Shih Che} and Kao, {Chia Wei} and Huang, {Yu Cheng} and Hsu, {Che Wei} and Chen, {Chia Hung}",

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AU - Kuo, Shih Che

AU - Kao, Chia Wei

AU - Huang, Yu Cheng

AU - Hsu, Che Wei

AU - Chen, Chia Hung

PY - 2021/7

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N2 - This letter presents a second-order incremental ADC (IADC) operated in three steps, which extends the performance of a second-order IADC close to that of a fourth-order IADC with only two amplifiers. It performs a second-order noise-shaping quantization in the first step operation. Reusing the same hardware, the circuit is reconfigured to perform fine quantization as a first-order IADC in the second and third step. Within a conversion time of 60 clock periods (oversampling ratio OSR = 60), 35 dB signal-to-quantization-noise ratio is boosted. The proposed topology is very suitable for low-bandwidth high-resolution data conversion.

AB - This letter presents a second-order incremental ADC (IADC) operated in three steps, which extends the performance of a second-order IADC close to that of a fourth-order IADC with only two amplifiers. It performs a second-order noise-shaping quantization in the first step operation. Reusing the same hardware, the circuit is reconfigured to perform fine quantization as a first-order IADC in the second and third step. Within a conversion time of 60 clock periods (oversampling ratio OSR = 60), 35 dB signal-to-quantization-noise ratio is boosted. The proposed topology is very suitable for low-bandwidth high-resolution data conversion.

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JO - Journal of Engineering

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A fourth-order incremental ADC in three-step

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