## Abstract

In this article, a digital LDO with a feedforward controller and weight redistribution algorithm (WRA) for line regulation improvement is proposed. The proposed digital low dropout (DLDO) uses a feedforward path to obtain the information of <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm{IN}}$</tex-math> </inline-formula> and applies WRA and body voltage controller to adjust <inline-formula> <tex-math notation="LaTeX">$I_{\mathrm{OUT}}$</tex-math> </inline-formula> to minimize the output voltage ripple <inline-formula> <tex-math notation="LaTeX">$\Delta V_{\mathrm{OUT}}$</tex-math> </inline-formula>. Different from conventional freeze mode, the feedforward control (FFC) with low quiescent current can keep <inline-formula> <tex-math notation="LaTeX">$\Delta V_{\mathrm{OUT}} <$</tex-math> </inline-formula> 0.5 mV in steady state and <inline-formula> <tex-math notation="LaTeX">$\Delta V_{\mathrm{OUT}} <$</tex-math> </inline-formula> 4 mV during line transient. In order for the feedback loop to rapidly wake up, the transient pump circuit is used to reduce the undershoot to less than 30 mV in the case of load change from 1 to 200 mA. Due to low quiescent current in the FFC, the DLDO achieves peak current efficiency of 99.99% at heavy loads.

Original language | English |
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Pages (from-to) | 1-11 |

Number of pages | 11 |

Journal | IEEE Journal of Solid-State Circuits |

DOIs | |

State | Accepted/In press - 2022 |

## Keywords

- Binary search algorithm
- body voltage control (BVC)
- Clocks
- digital low dropout (DLDO)
- feedforward control (FFC) technique
- line regulation
- Logic gates
- MOSFET
- power supply rejection (PSR)
- Regulators
- Switches
- Transient analysis
- Voltage control