A fast-locking all-digital phased-locked loop with a 1 ps resolution time-to-digital converter using calibrated time amplifier and interpolation digitally-controlled-oscillator

Hsing Chien Chu; Yi Hsiang Hua; Chung-Chih Hung

doi:10.1109/EDSSC.2016.7785286

A fast-locking all-digital phased-locked loop with a 1 ps resolution time-to-digital converter using calibrated time amplifier and interpolation digitally-controlled-oscillator

Hsing Chien Chu, Yi Hsiang Hua, Chung-Chih Hung

Department of Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

This paper presents an all-digital phase-locked loop (ADPLL) in the 0.18 pm CMOS process, which uses a multi-stage time-to-digital converter (TDC) with calibration and interpolation digitally-controlled-oscillator (IDCO). The ADPLL also utilizes a frequency tracking engine (FTE) to reduce the system locking time. The ADPLL has a frequency range of 149-1450 MHz, the minimum peak-to-peak jitter achieves 21.9 ps, and the TDC shows the minimum resolution of 1 ps. The power dissipation of the ADPLL is 18.2 mW at 800 MHz.

Original language	English
Title of host publication	2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	375-378
Number of pages	4
ISBN (Electronic)	9781509018307
DOIs	https://doi.org/10.1109/EDSSC.2016.7785286
State	Published - 15 Dec 2016
Event	2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016 - Hong Kong, Hong Kong Duration: 3 Aug 2016 → 5 Aug 2016

Publication series

Name	2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016

Conference

Conference	2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016
Country/Territory	Hong Kong
City	Hong Kong
Period	3/08/16 → 5/08/16

Keywords

All-digital phase-locked loop (ADPLL)
digitally-controlled-oscillator (DCO)
time amplifier (TA)
time-to-digital converter (TDC)

Access to Document

10.1109/EDSSC.2016.7785286

Cite this

Chu, H. C., Hua, Y. H., & Hung, C.-C. (2016). A fast-locking all-digital phased-locked loop with a 1 ps resolution time-to-digital converter using calibrated time amplifier and interpolation digitally-controlled-oscillator. In 2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016 (pp. 375-378). Article 7785286 (2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2016.7785286

Chu, Hsing Chien ; Hua, Yi Hsiang ; Hung, Chung-Chih. / A fast-locking all-digital phased-locked loop with a 1 ps resolution time-to-digital converter using calibrated time amplifier and interpolation digitally-controlled-oscillator. 2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 375-378 (2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016).

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title = "A fast-locking all-digital phased-locked loop with a 1 ps resolution time-to-digital converter using calibrated time amplifier and interpolation digitally-controlled-oscillator",

abstract = "This paper presents an all-digital phase-locked loop (ADPLL) in the 0.18 pm CMOS process, which uses a multi-stage time-to-digital converter (TDC) with calibration and interpolation digitally-controlled-oscillator (IDCO). The ADPLL also utilizes a frequency tracking engine (FTE) to reduce the system locking time. The ADPLL has a frequency range of 149-1450 MHz, the minimum peak-to-peak jitter achieves 21.9 ps, and the TDC shows the minimum resolution of 1 ps. The power dissipation of the ADPLL is 18.2 mW at 800 MHz.",

keywords = "All-digital phase-locked loop (ADPLL), digitally-controlled-oscillator (DCO), time amplifier (TA), time-to-digital converter (TDC)",

author = "Chu, {Hsing Chien} and Hua, {Yi Hsiang} and Chung-Chih Hung",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016 ; Conference date: 03-08-2016 Through 05-08-2016",

year = "2016",

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doi = "10.1109/EDSSC.2016.7785286",

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Chu, HC, Hua, YH & Hung, C-C 2016, A fast-locking all-digital phased-locked loop with a 1 ps resolution time-to-digital converter using calibrated time amplifier and interpolation digitally-controlled-oscillator. in 2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016., 7785286, 2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016, Institute of Electrical and Electronics Engineers Inc., pp. 375-378, 2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016, Hong Kong, Hong Kong, 3/08/16. https://doi.org/10.1109/EDSSC.2016.7785286

A fast-locking all-digital phased-locked loop with a 1 ps resolution time-to-digital converter using calibrated time amplifier and interpolation digitally-controlled-oscillator. / Chu, Hsing Chien; Hua, Yi Hsiang; Hung, Chung-Chih.
2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 375-378 7785286 (2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - This paper presents an all-digital phase-locked loop (ADPLL) in the 0.18 pm CMOS process, which uses a multi-stage time-to-digital converter (TDC) with calibration and interpolation digitally-controlled-oscillator (IDCO). The ADPLL also utilizes a frequency tracking engine (FTE) to reduce the system locking time. The ADPLL has a frequency range of 149-1450 MHz, the minimum peak-to-peak jitter achieves 21.9 ps, and the TDC shows the minimum resolution of 1 ps. The power dissipation of the ADPLL is 18.2 mW at 800 MHz.

AB - This paper presents an all-digital phase-locked loop (ADPLL) in the 0.18 pm CMOS process, which uses a multi-stage time-to-digital converter (TDC) with calibration and interpolation digitally-controlled-oscillator (IDCO). The ADPLL also utilizes a frequency tracking engine (FTE) to reduce the system locking time. The ADPLL has a frequency range of 149-1450 MHz, the minimum peak-to-peak jitter achieves 21.9 ps, and the TDC shows the minimum resolution of 1 ps. The power dissipation of the ADPLL is 18.2 mW at 800 MHz.

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Chu HC, Hua YH, Hung CC. A fast-locking all-digital phased-locked loop with a 1 ps resolution time-to-digital converter using calibrated time amplifier and interpolation digitally-controlled-oscillator. In 2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 375-378. 7785286. (2016 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2016). doi: 10.1109/EDSSC.2016.7785286

A fast-locking all-digital phased-locked loop with a 1 ps resolution time-to-digital converter using calibrated time amplifier and interpolation digitally-controlled-oscillator

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Keywords

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