A Fast 1-D Serial-Parallel Systolic Multiplier

I-Chen Wu*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

20 Scopus citations

Abstract

Based on the modified Booth's algorithm, a fast 1-D serial-parallel systolic multiplier is designed for multiplying two's complement numbers. The circuit with countercurrent data flow pattern accepts the multiplicand serially, the multiplier in parallel, and outputs the product serially. It requires a complementer and N/2cells, each of which contains a ripple-carry adder and some gates, where N is restricted to even. The number of clocks required to multiply an n-bit (n ≤ N) multiplier and an m-bit multiplicand is equal to n + m – 1, and independent of the circuit size N.

Original languageEnglish
Pages (from-to)1243-1247
Number of pages5
JournalIEEE Transactions on Computers
VolumeC-36
Issue number10
DOIs
StatePublished - 1 Jan 1987

Keywords

  • Countercurrent data flow pattern
  • five-level multiplexer
  • five-level recorder
  • modified Booth's Algorithm
  • systolic multiplier
  • two's complement, VLSI

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