A Fast 1-D Serial-Parallel Systolic Multiplier

I-Chen Wu

doi:10.1109/TC.1987.1676865

A Fast 1-D Serial-Parallel Systolic Multiplier

I-Chen Wu^*

^*Corresponding author for this work

Institute of Data Science and Engineering

Research output: Contribution to journal › Article › peer-review

21 Scopus citations

Abstract

Based on the modified Booth's algorithm, a fast 1-D serial-parallel systolic multiplier is designed for multiplying two's complement numbers. The circuit with countercurrent data flow pattern accepts the multiplicand serially, the multiplier in parallel, and outputs the product serially. It requires a complementer and N/2cells, each of which contains a ripple-carry adder and some gates, where N is restricted to even. The number of clocks required to multiply an n-bit (n ≤ N) multiplier and an m-bit multiplicand is equal to n + m – 1, and independent of the circuit size N.

Original language	English
Pages (from-to)	1243-1247
Number of pages	5
Journal	IEEE Transactions on Computers
Volume	C-36
Issue number	10
DOIs	https://doi.org/10.1109/TC.1987.1676865
State	Published - 1 Jan 1987

Keywords

Countercurrent data flow pattern
five-level multiplexer
five-level recorder
modified Booth's Algorithm
systolic multiplier
two's complement, VLSI

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10.1109/TC.1987.1676865

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AB - Based on the modified Booth's algorithm, a fast 1-D serial-parallel systolic multiplier is designed for multiplying two's complement numbers. The circuit with countercurrent data flow pattern accepts the multiplicand serially, the multiplier in parallel, and outputs the product serially. It requires a complementer and N/2cells, each of which contains a ripple-carry adder and some gates, where N is restricted to even. The number of clocks required to multiply an n-bit (n ≤ N) multiplier and an m-bit multiplicand is equal to n + m – 1, and independent of the circuit size N.

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A Fast 1-D Serial-Parallel Systolic Multiplier

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Keywords

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