A dual-band four-mode δ-Σ frequency synthesizer

Wei-Zen Chen*, Dai An Yu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations


This paper describes the design of a dual-band, four-mode Δ-Σ frequency synthesizer for WLAN a,b,g and Bluetooth applications. Integrating both a multi-modulus PLL and a 3rd order Δ-Σ modulator in a single chip, the channel spacing of the RF synthesizer can be as low as 20 kHz and the frequency hopping time is less than 67 μ sec. A new charge pump circuit is proposed to improve its linearity and the matching of the pumping currents. The measured phase noise at 1MHz offset are about -114 dBc/Hz and -116 dBc/Hz respectively at 5 GHz and 2.5 GHz frequency bands. Fabricated in a 0.18-μm CMOS process, the chip size is 1.95 mm2. The total power consumption is 19.54 mW from a 1.8 V power supply.

Original languageEnglish
Title of host publication2006 IEEE Radio Frequency Integrated Circuits(RFIC) Symposium - Digest of Papers
Number of pages4
StatePublished - 1 Dec 2006
Event2006 IEEE Radio Frequency Integrated Circuits Symposium - San Francisco, CA, United States
Duration: 11 Jun 200613 Jun 2006

Publication series

NameDigest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
ISSN (Print)1529-2517


Conference2006 IEEE Radio Frequency Integrated Circuits Symposium
Country/TerritoryUnited States
CitySan Francisco, CA


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