TY - GEN
T1 - A Digital Jitter Compensation Technique for Analog-to-Digital Converters
AU - Wang, Ding Hao
AU - Wu, Jieh Tsorng
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - For an ADC that periodically converts a time-varying analog input, the jitter in the ADC's sampling clock introduces sampling errors, degrading the ADC's dynamic performance. This paper describes a jitter compensation technique to mitigate the effect of sampling clock jitters. Clock jitter is detected by using an extra ADC that samples a reference clock. Sampling errors are then canceled by using a digital differentiator with the acquired jitter estimates. Experiment on a test chip shows that this technique improves the SNR performance of a 12-bit 247-MS/s ADC from 51.9 dB to 56.3 dB when the input is an 80-MHz -1-dBPS sinewave. A sampling clock with 4.89 ps rms jitter drives the ADC.
AB - For an ADC that periodically converts a time-varying analog input, the jitter in the ADC's sampling clock introduces sampling errors, degrading the ADC's dynamic performance. This paper describes a jitter compensation technique to mitigate the effect of sampling clock jitters. Clock jitter is detected by using an extra ADC that samples a reference clock. Sampling errors are then canceled by using a digital differentiator with the acquired jitter estimates. Experiment on a test chip shows that this technique improves the SNR performance of a 12-bit 247-MS/s ADC from 51.9 dB to 56.3 dB when the input is an 80-MHz -1-dBPS sinewave. A sampling clock with 4.89 ps rms jitter drives the ADC.
UR - http://www.scopus.com/inward/record.url?scp=85167653601&partnerID=8YFLogxK
U2 - 10.1109/ISCAS46773.2023.10182169
DO - 10.1109/ISCAS46773.2023.10182169
M3 - Conference contribution
AN - SCOPUS:85167653601
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 56th IEEE International Symposium on Circuits and Systems, ISCAS 2023
Y2 - 21 May 2023 through 25 May 2023
ER -