A design flow for multiplierless linear-phase fir filters: From system specification to verilog code

Kai Yuan Jheng; Shyh-Jye Jou; An Y. Wu

doi:10.1109/ISCAS.2004.1329520

A design flow for multiplierless linear-phase fir filters: From system specification to verilog code

Kai Yuan Jheng^*, Shyh-Jye Jou, An Y. Wu

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

21 Scopus citations

Abstract

This paper presents a design flow for the multiplierless linear-phase FIR filter synthesizer, which combines several research efforts. We propose a local search algorithm with variable filter order to reduce the number of adders further. In addition, several design techniques are adopted to reduce the hardware complexity of the system. By using this synthesizer, the system designers can design a filter efficiently and a chip can be successfully finished in a very short time.

Original language	English
Pages (from-to)	V-293-V-296
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	5
DOIs	https://doi.org/10.1109/ISCAS.2004.1329520
State	Published - 2004
Event	2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada Duration: 23 May 2004 → 26 May 2004

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10.1109/ISCAS.2004.1329520

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title = "A design flow for multiplierless linear-phase fir filters: From system specification to verilog code",

abstract = "This paper presents a design flow for the multiplierless linear-phase FIR filter synthesizer, which combines several research efforts. We propose a local search algorithm with variable filter order to reduce the number of adders further. In addition, several design techniques are adopted to reduce the hardware complexity of the system. By using this synthesizer, the system designers can design a filter efficiently and a chip can be successfully finished in a very short time.",

author = "Jheng, {Kai Yuan} and Shyh-Jye Jou and Wu, {An Y.}",

year = "2004",

doi = "10.1109/ISCAS.2004.1329520",

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note = "2004 IEEE International Symposium on Cirquits and Systems - Proceedings ; Conference date: 23-05-2004 Through 26-05-2004",

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AU - Jou, Shyh-Jye

AU - Wu, An Y.

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Y1 - 2004

N2 - This paper presents a design flow for the multiplierless linear-phase FIR filter synthesizer, which combines several research efforts. We propose a local search algorithm with variable filter order to reduce the number of adders further. In addition, several design techniques are adopted to reduce the hardware complexity of the system. By using this synthesizer, the system designers can design a filter efficiently and a chip can be successfully finished in a very short time.

AB - This paper presents a design flow for the multiplierless linear-phase FIR filter synthesizer, which combines several research efforts. We propose a local search algorithm with variable filter order to reduce the number of adders further. In addition, several design techniques are adopted to reduce the hardware complexity of the system. By using this synthesizer, the system designers can design a filter efficiently and a chip can be successfully finished in a very short time.

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U2 - 10.1109/ISCAS.2004.1329520

DO - 10.1109/ISCAS.2004.1329520

M3 - Conference article

AN - SCOPUS:4344575018

SN - 0271-4310

VL - 5

SP - V-293-V-296

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

Y2 - 23 May 2004 through 26 May 2004

ER -

A design flow for multiplierless linear-phase fir filters: From system specification to verilog code

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