@inproceedings{1937d597c5a049d69e7428177ca71ab9,
title = "A Design Flow for Micro Bump and Stripe Planning on Modern Chip-Package Co-Design",
abstract = "Micro bumps and stripes play essential roles for the transmission of signals and the preservation of power integrity in the modern flip-chip packaging process. For different placement block designs on a chip, the best micro bump arrangement and stripe generation method is usually varied accordingly. It often takes a lot of manpower and time cost in generating the delivery path of signal and power transmission in a package. As a result, we propose a way that can automatically generate a power delivery network (PDN) on the top metal layers in a chip and set the coordinate of micro bumps. It can solve the IR drop problem in the early stage, and decrease the integrated circuit (IC) and packaging layout design iteration, thus shorten time-to-market (TTM). Experimental results show that our flows can reduce IR drop to 5% of supply voltage in block.",
keywords = "flip chip, IR drop, k-means clustering, micro bump, power delivery network",
author = "Huang, {Ming Yu} and Hung-Ming Chen and Kuan-Neng Chen and Wu, {Shih Hsien} and Yu-Min Lee and Su, {An Yu}",
year = "2020",
month = jun,
doi = "10.1109/ECTC32862.2020.00348",
language = "English",
isbn = "978-1-7281-6181-5",
series = "Proceedings - Electronic Components and Technology Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "2236--2241",
booktitle = "Proceedings - IEEE 70th Electronic Components and Technology Conference, ECTC 2020",
address = "美國",
note = "70th IEEE Electronic Components and Technology Conference, ECTC 2020 ; Conference date: 03-06-2020 Through 30-06-2020",
}